Apparatus and method for an input stage of an operational amplifier

A method of reducing the offset voltage and circuit drift due to changes in the power supply and common mode voltages changes of an input stage of an operational amplifier while limiting voltages applied across transistors of said input stage, said method comprising the steps of:

• coupling a first transistor and a second transistor as a differential amplifier, said differential amplifier including a bias-setting resistor coupled across said first and said second transistors, load terminals of said first and said second transistors each having a first and a second plurality of serially-coupled load transistors respectively coupled thereto, a common terminal of said first and second transistors having a third plurality of series-coupled bias transistors coupled thereto;
• maintaining a first terminal of said bias-setting resistor at a first constant voltage using a feedback circuit responsive to a voltage level of said first terminal and a first ratio of a power supply voltage, said feedback circuit applying a control signal to a bias transistor;
• and
• maintaining a second terminal of said bias-setting resistor at a second constant voltage using said feedback circuit responsive to a voltage level of said first terminal and to a second ratio of said power supply voltage, said feedback circuit applying a control signal to a load transistor.

An input stage for an operational amplifier, said input stage comprising:

• a first circuit node;
• a second circuit node;
• a bias resistor coupled between said first and said second node;
• a first and a second input transistor, said first and second input transistor coupled between said first and said second node;
• a first plurality of transistors coupled between said first input transistor and a second power supply terminal;
• a second plurality of transistors coupled between said second input transistor and said second power supply terminal;
• a third plurality of transistors coupled between said first and second input transistors and a first power supply terminal;
• a current source coupled to said bias resistor;
• and,
• a feedback circuit interconnected with said first and said second plurality of transistors, said feedback circuit maintaining said second node at a constant voltage, said feedback circuit maintaining said first node at a constant voltage;
• wherein said feedback circuit includes a fourth plurality of transistors coupled in series between said first and said second power supply terminal;
• said feedback circuit including a first plurality of resistors coupled in series between said first and said second power supply terminals.