Probe for wafer burn-in test system

A test probe assembly for testing electronic integrated circuitry over a range of temperatures, comprising:

• a device interface board connectable to a source of test signals for transmitting test signals to and from the source;
• a probe guide comprising an upper guide element, a lower guide element and at least one spacer member for maintaining the upper guide element spaced apart from and in fixed relationship to the lower guide element, said upper and lower guide elements having a plurality of aligned holes therein, said aligned upper and lower guide elements each comprising a layer of silicon adjacent to a layer of electrically insulating, photolithographically patternable material, each of said layers of photolithographically patternable material having an inner surface facing one of said layers of silicon, each of said layers of silicon having an inner surface facing one of said layers of photolithographically patternable material, the adjacent layers of silicon and photolithographically patternable material in each of the upper and lower guide elements being joined by fused layers of metal deposited on each of said inner surfaces of photolithographically patternable material and each of said inner surfaces of silicon;
• and
• a plurality of probes, each probe having one end abutting said device interface board and having another end for contacting test points on electronic integrated circuitry to be tested, each of said plurality of probes extending completely through said holes in said upper and lower guide elements.

A method of forming a test probe assembly for environmentally testing electronic circuitry, comprising the steps of:

• providing first and second layers of silicon having an array of chemically etched holes therein;
• providing first and second layers of photolithographically patternable material having an array of chemically etched holes therein, said photolithographically patternable material array of holes having a similar pattern to said silicon array of holes;
• depositing a thin metallic film onto one side of each of said first and second layers of silicon;
• depositing a thin metallic film onto one side of each of said first and second layers of photolithographically patternable material;
• positioning said first layer of silicon with respect to said first layer of photolithographically patternable material so that said arrays of holes in each of said first layers are aligned and so that said thin metallic films deposited onto each of said first layers face each other;
• positioning said second layer of silicon with respect to said second layer of photolithographically patternable material so that said arrays of holes in each of said second layers are aligned and so that said thin metallic films deposited onto each of said second layers face each other;
• heat treating said positioned first layers and said positioned second layers so that said facing thin metallic films fuse to form a metallic bond;
• attaching said first layer of silicon to said second layer of silicon with at least one spacer to maintain said first layer of silicon spaced apart from and in fixed relationship to said second layer of silicon;
• providing a device interface board which is connectable to the apparatus for testing electronic circuitry and which carries test signals outputted by the apparatus;
• attaching a plurality of test probes to said device interface board, each of said test probes having a length greater than the combined widths of said spacer, said first and second photolithographically patternable material layers, and said first and second silicon layers;
• and
• inserting said extending test probes through said aligned arrays of holes in said positioned first layers and said positioned second layers to complete said test probe assembly.