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US 5,210,448 AGranted
Programmable logic device
AssigneeRicoh Company, Ltd.
InventorAkira Takata
Life of this patent
Estimating the term…
Abstract
A programmable logic device includes wordlines each having two sides for connection, bitlines substantially intersecting with the wordlines constituting an AND array portion in conjunction with the wordlines and a plurality of nonvolatile memory elements. Each nonvolatile memory element has data memorized therein and is connected to one of the wordlines and one of the bitlines. And the device has an OR array portion which conducts a predetermined calculation on the basis of the data read from the memory element, an input buffer circuit connected to one side of the wordlines and a decoder connected to the other side of the wordlines through a wordline driver.
Claims11
A programmable logic device comprising:
- an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at each cross point of said bitlines and said wordlines, each of said wordlines having two opposed terminals;
- means for reading data from said plurality of non-volatile memory elements;
- an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines;
- an input buffer connected to one of said terminals of said wordlines;
- a wordline driver connected to the other of said terminals of said wordlines;
- and
- a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array.
4 more elements
A programmable logic device operable in logic operation mode and in a program writing operation mode, said device comprising:
- an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto;
- means for reading data from said plurality of non-volatile memory elements;
- an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines;
- an input buffer connected to the other of said terminals of said wordlines;
- a wordline driver connected to the other of said terminals of said wordlines;
- a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array;
- first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source;
- second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source;
- and
- a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between said logic operation mode and said program writing operation mode.
7 more elements
A programmable logic device operable in logic operation mode and in a program writing operation mode, said device comprising:
- an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto;
- means for reading data from said plurality of non-volatile memory elements;
- an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines;
- an input buffer connected to one of said terminals of said wordlines;
- a wordline driver connected to the other of said terminals of said wordlines, and said wordline driver including feedback inverters each comprising a plurality of transistors connected in an inverter arrangement functioning as a positive feedback circuit in the logic operation mode;
- a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array;
- first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source;
- second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source;
- and
- a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between the logic operation mode and the program writing operation mode.
7 more elements
A programmable logic device operable in logic operation mode, in a program writing operation mode and in a test operation mode, said device comprising:
- an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto;
- means for reading data from said plurality of non-volatile memory elements;
- an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines;
- an input buffer connected to one of said terminals of said wordlines;
- a wordline driver connected to the other of said terminals of said wordlines;
- a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array;
- first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source;
- second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source;
- a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between the logic operation mode and the program writing operation mode;
- a source of a test control signal;
- and
- a test control terminal to which said test control signal is applied to cause the programmable logic device to operate in the test operation mode.
9 more elements
Dependencies are inferred from the claim text.