Power transistor monolithic integrated structure

A power transistor monolithic integrated chip structure, comprising a plurality of parallel connected transistor cells arranged in two rows within said chip structure;

• each of said transistor cells containing at least one component transistor and transistor electrode contacts, two rows of connection points mirror symmetrically arranged on an upper surface of said chip structure;
• branch conductors for connecting consecutive connection points in each row of connection points alternatingly to emitter and collector contacts of an assigned row of transistor cells;
• said rows of connection points extending along opposite edges of said chip structure;
• said rows of transistor cells being spaced apart at a distance corresponding at least to a thickness of said chip structure;
• power supply conductors arranged between said two rows of transistor cells;
• and protective circuits against overvoltage of avalanche diodes arranged between said rows of said transistor cells.

A power transistor monolithic integrated chip structure, comprising a plurality of parallel connected transistor cells arranged in two rows within said chip structure;

• each of said transistor cells containing at least one component transistor and transistor electrode contacts, two rows of connection points mirror symmetrically arranged on an upper surface of said chip structure;
• branch conductors for connecting consecutive connection points in each row of connection points alternatingly to emitter and collector contacts of an assigned row of transistor cells;
• said rows of connection points extending along opposite edges of said chip structure;
• wherein each of said transistor cells has an elongated configuration and includes an elongated base zone, a base contact, emitter diffusion zones at each side of the base contact, pinch resistors arranged between the base contact and the emitter diffusion zones and being provided with additional emitter diffusion zones;
• said pinch resistors and said additional emitter diffusion zones increasing in width toward the center of the transistor cell to stabilize a current density in an emitter of the transistor when operating in a linear range.

A power transistor monolithic integrated chip structure, comprising a plurality of parallel connected transistor cells arranged in two rows within said chip structure;

• each of said transistor cells containing at least one component transistor and transistor electrode contacts, two rows of connection points mirror symmetrically arranged on an upper surface of said chip structure;
• branch conductors for connecting consecutive connection points in each row of connection points alternatingly to emitter and collector contacts of an assigned row of transistor cells;
• said rows of connection points extending along opposite edges of said chip structure;
• wherein each of said transistor cells has an elongated configuration and includes an elongated emitter having an emitter contact window and a superimposed emitter metallization;
• and further comprising a resistor layer of a doped polysilicon arranged between the emitter contact window and the superposed emitter metallization to stabilize a current density in the emitter when operating in a linear range.

A power transistor monolithic integrated chip structure, comprising a plurality of parallel connected transistor cells arranged in two rows within said chip structure;

• each of said transistor cells containing at least one component transistor and transistor electrode contacts, two rows of connection points mirror symmetrically arranged on an upper surface of said chip structure;
• branch conductors for connecting consecutive connection points in each row of connection points alternatingly to emitter and collector contacts of an assigned row of transistor cells;
• said rows of connection points extending along opposite edges of said chip structure;
• each transistor cell having an elongated configuration defining a longitudinal axis;
• and portions of the transistor cell subject to a lower current density extend in a center region of the transistor cell along said longitudinal axis whereas other portions of the transistor cell subject to a higher current density extend in cooler marginal parts of the transistor cell.

A power transistor monolithic integrated chip structure, comprising a plurality of parallel connected transistor cells arranged in two rows within said chip structure;

• each of said transistor cells containing at least one component transistor and transistor electrode contacts, two rows of connection points mirror symmetrically arranged on an upper surface of said chip structure;
• branch conductors for connecting consecutive connection points in each row of connection points alternatingly to emitter and collector contacts of an assigned row of transistor cells;
• said rows of connection points extending along opposite edges of said chip structure;
• each of said transistor cells includes a plurality of the component transistors, each of the component transistors being operated with a different current density, so that a group of the component transistors subject to a lower current density than a remaining portion of the component transistors are arranged in a warmer central part of the transistor cell and the remaining portion of the component transistors operating at a higher current density are arranged in cooler marginal parts of the transistor cell.

A power transistor monolithic integrated chip structure, comprising a plurality of parallel connected transistor cells arranged in two rows within said chip structure;

• each of said transistor cells containing at least one component transistor and transistor electrode contacts, two rows of connection points mirror symmetrically arranged on an upper surface of said chip structure;
• branch conductors for connecting consecutive connection points in each row of connection points alternatingly to emitter and collector contacts of an assigned row of transistor cells;
• said rows of connection points extending along opposite edges of said chip structure;
• and a measuring resistor arranged between an emitter conductor and an emitter connection spot in each of the transistor cells to measure emitter current for use in current regulation or current limitation.

A power transistor monolithic integrated chip structure, comprising a plurality of parallel connected transistor cells arranged in two rows within said chip structure;

• each of said transistor cells containing at least one component transistor and transistor electrode contacts, two rows of connection points mirror symmetrically arranged on an upper surface of said chip structure;
• branch conductors for connecting consecutive connection points in each row of connection points alternatingly to emitter and collector contacts of an assigned row of transistor cells;
• said rows of connection points extending along opposite edges of said chip structure;
• said transistor cells being electrically insulated from each other and each having a metallized branch conductor leading from a collector connection spot to a collector connection point on the upper surface of the chip structure, said collector branch conductor having a narrow portion which, when an assigned transistor cell is damaged, burns up and separates the collectors of the other transistor cells from the assigned transistor cell which has been damaged.