MOS device having a well layer for controlling threshold voltage
AssigneeKabushiki Kaisha Toshiba
InventorsShizuo Sawada, Seiko Iwasaki
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Abstract
The present invention provides a semiconductor device having a well, formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.
Claims15
A MOS device comprising:
- a semiconductor substrate of a first conductivity type having a major surface;
- a first insulating film on said major surface to define a MOS transistor region;
- a MOS transistor in said MOS transistor region including source and drain layers of a second conductivity type in said major surface and a gate electrode spaced from a channel region between said source and drain layers by a gate insulating film thinner than said first insulating film;
- and
- a well layer formed in and extending below said channel region to control a threshold voltage of said MOS transistor, said well layer having a substantially semi-circular section with a non-flat lower surface and non-flat sides.
A MOS device comprising:
- a semiconductor body having a major surface;
- a first insulating film on said major surface to define a MOS transistor region;
- a MOS transistor in said MOS transistor region having a source layer and a drain layer formed in said semiconductor body to define a channel region therebetween, and a gate electrode spaced from said channel region by a gate insulating film thinner than said first insulating film;
- and
- at least one well layer formed in and extending below said channel region to control a threshold voltage of said MOS transistor, said well layer having a substantially semicircular and continuously curved cross-section.
A MOS device comprising:
- a semiconductor body having a major surface;
- a first insulating film on said major surface to define a MOS transistor region;
- a plurality of MOS transistors respectively formed in said MOS transistor regions, each MOS transistor comprising a source layer and a drain layer formed in said semiconductor body to define a channel region therebetween, and a gate electrode spaced from said channel region by a gate insulating film thinner than said first insulating film;
- and
- well layers formed in and extending below said channel regions to control respective threshold voltages of said MOS transistor, said well layers having substantially semicircular and continuously curved cross-sections.
A MOS device comprising:
- a semiconductor body;
- a MOS transistor having a source layer and a drain layer formed in said semiconductor body to define a channel region therebetween, and a gate electrode insulatively spaced from said channel region;
- and
- at least two well layers formed in said channel region to control a threshold voltage of said MOS transistor.
A MOS device, comprising:
- a semiconductor body having a major surface;
- first and second MOS transistors respectively formed in first and second MOS transistor regions on said major surface;
- a first arrangement of well layers in a channel region of said first MOS transistor to set a threshold voltage of said first MOS transistor;
- and
- a second arrangement of well layers in a channel region of said second MOS transistor to set a threshold voltage of said second MOS transistor which is different than the threshold voltage of said first MOS transistor.
Dependencies are inferred from the claim text.