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US 5,210,236 AGranted
Differential amplifier
AssigneeKabushiki Kaisha Toshiba
InventorToshinari Takayanagi
Life of this patent
Estimating the term…
Abstract
A differential amplifier has a pair of inputs and a pair of outputs. Each of the outputs is connected between a high potential source and a low potential source through a pair of FETs, respectively. These FETs have the same conduction type. A gate of one of the FETs is connected to one of the inputs, and a gate of the other FET is connected to the other input. This arrangement suppresses output offset and realizes a wide sensitivity range.
Claims14
A differential amplifier comprising:
- a first potential source;
- a second potential source;
- a first FET connected to said first potential source;
- a second FET connected to said second potential source;
- a third FET connected to said first potential source;
- a fourth FET connected to said second potential source;
- a first output terminal connected directly to a junction between said first and second FETs;
- a second output terminal connected directly to a junction between said third and fourth FETs;
- a first input terminal connected to gates of the first and fourth FETs;
- and
- a second input terminal connected to gates of the second and third FETs,
- wherein an ON state at said second FET is weakened and an ON state at said fourth FET is strengthened when a high potential and a low potential are loaded in said first input terminal and said second input terminal, respectively, so that a current flows from said second potential source to said second output terminal, thus increasing an amplifying efficiency of said differential amplifier.
9 more elements
A differential amplifier comprising:
- a first potential source;
- a second potential source providing a higher potential than said first potential source;
- a first N-type FET connected to said first potential source through a constant current source;
- a second N-type FET connected to said second potential source;
- a third N-type FET connected to said first potential source through said constant current source;
- a fourth N-type FET connected to said second potential source;
- a fifth FET which serves as said constant current source;
- a first output terminal connected to a gate of said fifth FET;
- a second output terminal connected directly to a junction between said third and fourth N-type FETs;
- a first input terminal connected to gates of said first and fourth FETs;
- and
- a second input terminal connected to gates of said second and third FETs,
- wherein said second and fourth FETs are depletion FETs, and said first and third FETs are enhancement FETs.
10 more elements
Dependencies are inferred from the claim text.