Solid state imaging element with bus breakage detector

A solid state imaging element comprising:

• a plurality of photodetectors arranged in a two-dimensional array on a semiconductor substrate;
• a plurality of MOS transistors for reading out signal charges and connected with respective photodetectors;
• first and second scanner circuits respectively disposed in a vertical direction and a horizontal direction for controlling reading out of signal charges;
• a plurality of bus lines disposed along the vertical and the horizontal directions connecting said MOS transistors with said scanner circuits;
• and
• at least one bus line breakage checking means for the vertical direction and one bus line breakage checking means for the horizontal direction, each bus line breakage checking means including a plurality of second transistors connected in series with respective vertical direction and horizontal direction bus lines, a test pad connected with said second transistors through said bus lines, and a voltage applying pad connected to said second transistors for applying a voltage to control switching of said second transistors.

A solid state imaging element comprising:

• a plurality of photodetectors arranged in a two-dimensional array on a semiconductor substrate;
• first and second circuits for reading out signal charges in a vertical direction and a horizontal direction, respectively;
• a plurality of gated transistors for controlling charge transfer from respectively photodetectors to said first and second circuits;
• a scanner for controlling the switching of said gated transistors;
• a plurality of bus lines in a transverse direction and a plurality of bus lines in a longitudinal direction respectively connecting gated transistors with said scanner;
• and
• at least one bus line breakage checking means including a plurality of second transistors for connecting said bus lines in a transverse direction in series and for connecting said bus lines in a longitudinal direction in series, two test pads disposed at and connected to respective ends of said bus lines through said second transistors, and a gate voltage applying pad connected to said transistors for applying a voltage to control switching of said second transistors.