Symbol synchronizer for sampled signals

A symbol synchronizer, comprising:

• one-bit quantization means for receiving a sampled baseband signal in a predetermined digital signalling format and generating a binary-valued data sequence therefrom;
• level-transition detection means for detecting logic level transitions in said binary-valued data sequence, said level-transition detection means including logic means for masking transitions in said data sequence that do not occur at a predetermined timing offset from the symbol timing epochs thereof and for generating a transition pulse sequence comprising logic pulses at the symbol rate of said data sequence and at said predetermined timing offset from the symbol timing epochs, said predetermined timing offset being on the interval ##EQU7## depending on said digital signalling format, where T is the symbol period;
• and
• a binary-quantized digital phase-locked loop for receiving the transition pulse sequence from said level-transition detection means and generating a stable symbol clock therefrom, said phase-locked loop including:
• (a) a digitally controlled oscillator for generating a symbol clock signal;
• (b) phase detecting means for comparing the symbol clock signal from said digitally controlled oscillator to the transition pulse sequence from said level-transition detection means, said phase detecting means including counting means for determining the timing difference between the symbol clock signal and the pulses of the transition pulse sequence, said counting means being enabled by the symbol clock pulses, and said counting means being reset by the transition pulse sequence, said phase detecting means further including count decoding means for receiving said timing difference from said counting means and generating a lead signal if the symbol clock leads the transition pulse sequence and generating a lag signal if the symbol clock lags the transition pulse sequence;
• and
• (c) a random walk filter for receiving the lead and lag signals from said phase detecting means, said filter including an up/down counting means for incrementing a filter count upon receipt of a lag signal and for decrementing a filter count upon receipt of a lead signal, said filter further including count decoding means for receiving said filter count and generating advance and retard signals to said digitally controlled oscillator for respectively advancing and retarding the phase of the symbol clock based on said timing difference.

A method for deriving a symbol clock reference from a sampled signal, comprising:

• generating a binary-valued data sequence from a sampled baseband signal in a predetermined digital signalling format;
• detecting logic level transitions in said binary-valued data sequence by masking transitions in said data sequence that do not occur at a predetermined timing offset from the symbol timing epochs thereof and generating a transition pulse sequence comprising logic pulses at the symbol rate of said data sequence and at said predetermined timing offset from the symbol timing epochs, said predetermined timing offset being on the interval ##EQU8## depending on said digital signalling format, where T is the symbol period;
• and
• providing said transition pulse sequence to a binary-quantized digital phase-locked loop for generating a stable symbol clock therefrom.