Clock signal multiplier
AssigneeNational Semiconductor Corporation
InventorsDennis L. Wendell, Charles Hochstedler, Dan Lunecki, Terry L. Lyon
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Abstract
A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.
Claims18
In an integrated circuit having at least a first internal clock signal line, apparatus for selectably translating a clock signal to a higher-frequency clock signal, comprising:
- input means for receiving a first clock signal;
- multiplier means for receiving said clock signal from said input means and outputting a second clock signal having a higher frequency than said first clock signal;
- means for adjusting the frequency of said second clock signal;
- and
- multiplexer means for selectably placing one of said first clock signal and said second clock signal on said internal clock signal line.
In an integrated circuit having at least a first internal clock signal line, said integrated circuit having a normal operating frequency, apparatus for selectably translating a clock signal to a higher-frequency clock signal, comprising:
- input means for receiving a first clock signal, said first clock signal having a frequency less than said normal operating frequency;
- multiplier means for receiving said first clock signal from said input means and outputting a second clock signal having a frequency substantially equal to said normal clock frequency, said multiplier means comprising a plurality of series-connected one-shots, each of said plurality of one-shots including means for receiving an analogue signal for adjusting the pulse-width of the one-shot;
- means for monitoring the frequency of said second clock signal and providing said analogue signal;
- and
- multiplexer means for selectably placing one of said first clock signal and said second clock signal on said internal clock signal line;
- said input means, said multiplier means and said multiplexer means being provided on a single integrated circuit chip wherein said integrated circuit chip is a memory chip including means for storing data in a plurality of addressable memory locations.
In an integrated circuit having at least a first internal clock signal line, a method for translating a clock signal to a higher-frequency clock signal, comprising:
- receiving a first clock signal;
- multiplying said received clock signal and outputting a second clock signal having a higher frequency than said first clock signal;
- adjusting the frequency of said second clock signal;
- and
- selecting, in response to a selection signal, one of said first clock signal and said second clock signal for placing on said internal clock signal line.
In an integrated circuit having at least a first internal clock signal line, apparatus for selectively translating a clock signal to a higher-frequency clock signal, comprising:
- input means for receiving a first clock signal;
- multiplier means for receiving said first clock signal from said input means and outputting a second clock signal having a higher frequency than said first clock signal;
- a multiplexer having at least a first, second, and third input signal and an output signal, said first input signal being said first clock signal, said second input signal being said second clock signal, said third input signal being a control signal for said multiplexer, said output signal being said first input signal when said control signal is in a first state and said output signal being said second input signal when said control signal is in a second state.
Dependencies are inferred from the claim text.