Apparatus for decoding BCH code

Abstract

An apparatus for decoding BCH code having first, second and third circuits for generating a syndrome S1, a syndrome S3 and a parity P, respectively from a receiving sequence, a fourth circuit coupled to the first circuit for generating S1.sup.2 from the syndrome S1, a fifth circuit coupled to the first circuit, second circuit and fourth circuit for generating (S1.sup.3 +S3), a Chien search circuit which includes a first generating circuit supplied with the S1 and S1.sub.2 for generating a first stage of error-location polynomial A, where A=S1.alpha..sup.-2n +S1.sup.2 .alpha..sup.-n, and a second generating circuit supplied with the (S1.sup.3 .alpha.+S3) and the A for generating a second stage of error-location polynomial B, wherein B=A+S1.sup.3 +S3, and an error correction and detection logic circuit supplied with the S1, P, (S1.sup.3 +S3), A and B and with a decode selection signal and a BCH code selection signal for generating an error correction or detection signal.

Dependencies are inferred from the claim text.