Memory unit delay-compensating circuit

A memory unit comprising:

• an array of memory cells;
• word lines connected to the memory cells;
• bit lines connected to the memory cells;
• a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2;
• delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal;
• means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal;
• and
• means for precharging the bit lines at a timing determined by the control signal;
• wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means includes a delay causing component substantially identical in structure to a part of the decoder causing variation in the time t2, thereby to adjust the time "t" to compensate for the variation of the time t2.

A memory unit comprising:

• an array of memory cells;
• word lines connected to the memory cells;
• a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2;
• delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal;
• and
• means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal;
• wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means includes a delay causing component substantially identical in structure to a part of the decoder causing variation in the time t2, thereby to adjust the time "t" to compensate for the variation of the time t2.

A memory unit comprising:

• an array of memory cells which has a capacity of n-words by m-bits where the characters "m" and "n" denote preset natural numbers;
• word lines connected to the memory cells;
• bit lines connected to the memory cells;
• a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal and having k-bits where the character "k" denotes a preset natural number which satisfies a relationship as "2.sup.k .gtoreq.n", the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to variation;
• delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal;
• means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal;
• and
• means for precharging the bit lines at a timing determined by the control signal;
• wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

A memory unit comprising:

• an array of memory cells;
• word lines connected to the memory cells;
• bit lines connected to the memory cells;
• a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to variation;
• delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal;
• means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal;
• and
• means for precharging the bit lines at a timing determined by the control signal;
• wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for the adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

A memory unit comprising:

• an array of memory cells;
• work lines connected to the memory cells;
• a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to an variation;
• delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal;
• and
• means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal;
• wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

In a memory unit including an array of memory cells;

• a plurality of word lines connected to the memory cells;
• a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2;
• access means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal, and
• a control circuit for controlling timing of activating a selected one of said word lines, the improvement comprising:
• generating means for generating a control signal for activating said access means,
• said generating means including timing means for providing a transition in said control signal at a time different by a preset time "t" for a corresponding transition in said clock signal,
• wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0,
• thereby to speed up activation of the selected work line and transfer of data.

A memory unit for use in combination with an address signal output circuit which latches an original address signal in response to the clock signal, the memory unit comprising:

• an array of memory cells which has a capacity of n-words by m-bits where the characters "m" and "n" denote preset natural numbers;
• word lines connected to the memory cells;
• bit lines connected to the memory cells;
• a decoder receiving an address signal from the address signal output circuit at a timing which follows a timing of an occurrence of a clock signal by a given time t1 which is determined by a signal delay time in the address signal output circuit, the address signal being in synchronism with the clock signal and having k-bits where the character "k" denotes a preset natural number which satisfies a relationship as "2.sup.k .gtoreq.n", the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2;
• delaying means for delaying the clock signal by a preset time "t" thereby converting the clock signal into a control signal;
• means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal;
• and
• means for precharging the bit lines at a timing determined by the control signal;
• wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, wherein the delaying means comprises a first delay causing circuit portion and a second delay causing circuit portion, wherein the first delay causing circuit portion of the delaying means has a substantially identical structure to a third circuit portion of the decoder for adjusting the time "t" in accordance with variation of the time t2 caused by the third circuit portion, thereby to compensate for the variation of the time t2, and wherein the second delay causing circuit portion of the delaying means has a substantially identical structure to a fourth circuit portion of the address signal output circuit for adjusting the time "t" in accordance with an variation of the time t1 caused by the fourth circuit portion, thereby to compensate for the variation of the time t1.