US 5,208,782 AGranted

Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement

AssigneesHitachi, Ltd., Hitachi VLSI Engineering Corp.

InventorsToshiyuki Sakuta, Masamichi Ishihara, Kazuyuki Miyazawa, Masanori Tazunoki, Hidetoshi Iwai, Hisashi Nakamura, Yasushi Takahashi, Toshio Maeda, Hiromi Matsuura, Ryoichi Hori, Toshio Sasaki, Osamu Sakai, Hiroyuki Uchiyama, Eiji Miyamoto, Kazuyoshi Oshima, Yasuhiro Kasama

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Abstract

A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

Claims28

Dependent claims

A semiconductor integrated circuit device comprising:

a first memory block formed in a main surface of a semiconductor chip, which includes a first memory array having memory cells arranged in a matrix form, a first address decoder coupled to said first memory array and a first data input/output circuit coupled to said first memory array;
a second memory block formed in said main surface of said semiconductor chip, which includes a second memory array having memory cells arranged in a matrix form, a second address decoder coupled to said second memory array and a second data input/output circuit coupled to said second memory array;
a first external terminal formed in said main surface of said semiconductor chip, to provide an external connection point for internal elements of said first memory block, said first external terminal being formed to be closer to the first memory block than to the closet peripheral edge of the semiconductor chip to shorten the connection distance between the first external terminal and the first memory block;
a second external terminal formed in said main surface of said semiconductor chip, to provide an external connection point for internal elements of said second memory block, said second external terminal being formed to be closer to the second memory block than to the closest peripheral edge of the semiconductor to shorten the connection distance between the second external terminal and the second memory block;
a lead attached on said main surface of said semiconductor chip via an insulator;
a first bonding wire for coupling said lead and said first external terminal;
and
a second bonding wire for coupling said lead and said second external terminal,
wherein said lead crosses a peripheral edge of the chip to extend from outside of said chip to the interior of said chip, wherein said lead has a first end located over the interior of said chip, and wherein at least one of said first and second bonding wires extends from a portion of said lead located over the interior of said chip, other than the first end of said lead, to shorten the distance for the connection between the lead and the corresponding first or second external terminal.

6 more elements

A semiconductor integrated circuit device comprising:

a first memory block formed in a main surface of a semiconductor chip, which includes a first memory array having memory cells arranged in a matrix form, a first address decoder coupled to said first memory array and a first data output circuit coupled to said first memory array;
a second memory block formed in said main surface of said semiconductor ship, which includes a second memory array having memory cells arranged in a matrix form, a second address decoder coupled to said second memory array and a second data output circuit coupled to said second memory array;
a first external terminal formed in said main surface of said semiconductor chip, to provide an external connection point for internal elements of said first memory, said first external terminal being formed to be closer to the first memory block than to the closest peripheral edge of the semiconductor chip to shorten the connection distance between the first external terminal and the first memory block;
a first lead attached on said main surface of said semiconductor chip via an insulator;
a first coupling means for coupling said first lead and said first external terminal;
and
a second coupling means for coupling said first lead and said second external terminal,
wherein said lead crosses a peripheral edge of the chip to extend from outside of said chip to the interior of said chip, wherein said lead has a first end located over the interior of said chip, and wherein at least one of the first and second coupling means extends from a portion of said lead located over the interior of said chip, other than the first end of said lead, to shorten the distance for connection between the lead and the corresponding first or second coupling means.

5 more elements

A semiconductor integrated circuit device comprising:

a plurality of memory blocks formed in a main surface of a semiconductor chip, each of which includes a memory array having memory cells arranged in a matrix form, an address decoder coupled to said memory array and a data output circuit coupled to said memory array;
a plurality of external terminal groups formed in said main surface of said semiconductor chip, each of which external terminals corresponds to a respective one of said memory blocks to provide an external connection point for internal elements of its corresponding memory block, and each of which is closer to its corresponding memory block than to the closest peripheral edge to shorten the connection distances between the external terminals and their corresponding memory blocks;
first and second leads attached on said main surface of said semiconductor chip via an insulator;
a first coupling means for coupling said first lead and said external terminals which belong to different external terminal groups to each other;
and
a second coupling means for coupling said second lead and said external terminals which belong to different external terminal groups to each other,
wherein said first and second leads each cross a peripheral edge of the chip to extend from outside of the chip to the interior of the chip, wherein each of the first and second leads has a first end located over the interior of said chip, wherein said first coupling means extends from a portion of the first lead, other than the first end thereof, to shorten the distance for connection between the first lead and one of the plurality of external terminals, and wherein the second coupling means extends from a portion of a second lead, other than the first end thereof, to shorten the distance for connection between the second lead and another one of the plurality of external terminals.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/892,708Filed 29 May 1992 · continuation
Priority: JP 1-301969 Feb 1989
Granted: 4 May 1993
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 29/808
With improved layout: using a flexible replacement scheme
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
G11C 29/88
Masking faults in memories by using spares or by reconfiguring: with partially good memories
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells