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US 5,208,779 AGranted
Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs
AssigneeMicron Technology, Inc.
InventorsTerry R. Walther, Scott E. Schaefer
Life of this patent
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Abstract
The invention is a circuit for synchronizing the refresh cycles of a bank of self-refreshing interruptable DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing interruptable DRAM to its respective external refresh pin.
Claims40
A memory bank having a plurality of random access memories, comprising:
- a) an internal refresh circuit for each of said random access memories, each said internal refresh circuit, when actuated, providing memory preservation to at least one of said random access memories;
- b) a bi-directional external refresh pin for each of said random access memories, each of said bi-directional external refresh pins capable of receiving a refresh message and said refresh message generated by one of said random access memories;
- c) a common node in electrical communication with each of said bi-directional external refresh pins;
- and
- d) said random access memories interacting one with the other through said common node such that when one of said random access memories generates said refresh message all of said plurality of random access memories are refreshed in response to said refresh message.
2 more elements
A random access memory, comprising:
- a) an internal refresh circuit, when actuated, capable of providing memory preservation to said random access memory;
- b) a bi-directional external refresh pin connectable to a common node, said bi-directional external refresh pin capable of receiving a refresh message and communicating said refresh message from and to said common node respectively;
- c) a timing circuit for determining a refresh cycle, said refresh cycle having a timing sequence for a periodic refresh rate;
- d) an arbitration circuit capable of enabling and disabling said internal refresh circuit and capable of generating said refresh message in response to a signal from said timing circuit and capable of receiving said refresh message;
- and
- e) said random access memory capable of interacting with at least one other random access memory, said random access memories communicating through said common node such that when one of said internal refresh circuits of one of said random access memories is activated said random access memory in electrical communication with said common node is refreshed in response to said refresh message.
3 more elements
Dependencies are inferred from the claim text.