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US 5,208,774 AGranted
Semiconductor memory device with low power consumption output data selector
AssigneeNEC Corporation
InventorYasuo Shibue
Life of this patent
Estimating the term…
Abstract
A static random access memory device has read-out bit lines for propagating read-out data bits to a selector circuit, and logic gates are coupled between the read-out bit lines and the selector circuit for inverting the data bits, wherein through current tends to flow through the logic gates due to decayed voltage levels on the read-out bit lines; however, only one of the logic gate coupled with a transfer transistor selected by a column address decoder is enabled so as to decrease the amount of the through current.
Claims7
A random access memory device fabricated on a single semiconductor chip and having at least a read-out phase of operation, comprising:
- a) a plurality of word lines selectively shifted to an active level depending upon row address bits;
- b) a plurality of read-out bit lines;
- c) a plurality of memory cells arranged in rows and columns, and associated with said plurality of word lines and with said plurality of read-out bit lines, each of said plurality of memory cells having a data storage circuit for storing a data bit, an inverting circuit for producing the complementary bit of said data bit, and a first field effect transistor coupled between first and second sources of voltage level and gated by said associated word line for transferring said complementary bit to said associated read-out bit line;
- and
- d) selecting means having a plurality of logic circuits coupled between said first and second sources of voltage level and operative to retrieve said data bits from said complementary bits on said read-out bit lines, respectively, and a plurality of second field effect transistors coupled between said plurality of logic circuits and an output data circuit and selectively turning on depending upon column address bits, said plurality of logic circuits being further operative to block output nodes thereof from one of said first and second sources of voltage level except for at least one of said logic gates associated with at least one of the second field effect transistors in on-state in a read-out phase of operation.
2 more elements
A random access memory device fabricated on a single semiconductor chip and having at least a write-in phase and a read-out phase of operation, comprising:
- a) a plurality of word lines one of which is shifted to an active level on the basis of row address bits;
- b) a plurality of write-in bit line pairs;
- c) a plurality of read-out bit lines;
- d) a plurality of write enable signal lines;
- e) a plurality of memory cells arranged in rows and columns, the rows of said plurality of word lines being respectively associated with said word lines, the columns of said plurality of memory cells being associated with said plurality of read-out bit lines, said plurality of write-in bit line pairs and said plurality of write enable signal lines, each of said plurality of memory cells having a flip flop circuit having a pair of memory nodes for memorizing a data bit in the form of a difference in voltage level, a first pair of transfer transistors respectively coupled with said pair of memory nodes and gated by the associated word line, a second pair of transfer transistors coupled between said first pair of transfer transistors and the associated write-in bit line pair and gated by the associated write enable signal line, a first inverting circuit coupled at the input node thereof with one of said pair of memory nodes for producing the complementary bit of said data bit memorized in said flip flop circuit, and a first transistor coupled between said first inverting circuit and the associated read-out bit line and gated by said associated word line;
- f) NOR gates having first input nodes respectively coupled to said plurality of read-out bit lines, and second input nodes supplied with a control signal shifted to an active low level in said read-out phase, said control signal being shifted to an inactive high level in said write-in phase;
- and
- g) a column selecting circuit having a plurality of second transistors coupled between the associated output nodes of said NOR gates and an output data unit and selectively shifted between on-state and off-state depending upon column address bits.
5 more elements
A random access memory device fabricated on a single semiconductor chip and having at least a write-in phase and a read-out phase of operation, comprising:
- a) a plurality of word lines one of which is shifted to an active level on the basis of row address bits;
- b) a plurality of write-in bit line pairs;
- c) a plurality of read-out bit lines;
- d) a plurality of write enable signal lines;
- e) a plurality of memory cells arranged in rows and columns, the rows of said plurality of word lines being respectively associated with said word lines, the columns of said plurality of memory cells being associated with said plurality of read-out bit lines, said plurality of write-in bit line pairs and said plurality of write enable signal lines, each of said plurality of memory cells having a flip flop circuit having a pair of memory nodes for memorizing a data bit in the form of a difference in voltage level, a first pair of transfer transistors respectively coupled with said pair of memory nodes and gated by the associated word line, a second pair of transfer transistors coupled between said first pair of transfer transistors and the associated write-in bit line pair and gated by the associated write enable signal line, a first inverting circuit coupled at the input node thereof with one of said pair of memory nodes for producing the complementary bit of said data bit memorized in said flip flop circuit, and a first transistor coupled between said first inverting circuit and the associated read-out bit line and gated by said associated word line;
- f) a plurality of series combinations of complementary inverting circuits and third transistors each coupled between first and second sources of power voltage levels, said complementary inverting circuits being controlled by said read-out bit lines, respectively, said third transistors selectively shifted between on-state and off-state depending upon column address bits;
- and
- g) a column selecting circuit having a plurality of fourth transistors coupled between the associated output nodes of said complementary inverting circuits and an output data unit, each of said fourth transistors being selectively shifted to the same state as the associated third transistor depending upon said column address bits.
5 more elements
Dependencies are inferred from the claim text.