Semiconductor memory device having bit lines and word lines different in data reading and data writing

A semiconductor memory device comprising:

• a plurality of memory cells (1) arranged in a plurality of columns,
• a plurality of reading bit lines (4) each corresponding to said respective one of said columns,
• selecting means (114) for selecting one of said reading bit lines for a predetermined period,
• precharging means (7) corresponding to each of said reading bit lines (4) for precharging said corresponding reading bit lines, and
• activating means (114) for activating one of said precharging means (7) corresponding to the selected reading bit line for only said predetermined period.

A serial access semiconductor memory device comprising:

• a plurality of memory cells (1) arranged in a matrix of rows and columns,
• a writing word line (5) corresponding to each row of memory cells (1) and a writing bit line (3) corresponding to each column of memory cells (1) for selectively writing information to said memory cells (1);
• a reading word line (6) corresponding to each row of memory cells (1) and a reading bit line (4) corresponding to each column of memory cells (1) for selectively reading information from said memory cells (1),
• each memory cell (1) comprising a writing transistor (14), a storage capacitor (17), a storage transistor (15) and a reading transistor (16),
• selecting means (9) for sequentially selecting one of said reading bit lines (4) for a predetermined time period,
• precharging means (7) corresponding to each of said reading bit lines (4) for precharging said bit lines (4),
• first activating means (9) for activating the precharging means (7) corresponding to the selected bit line for a predetermined portion of said predetermined time period,
• switching means (8) connected to said bit lines (4) for extracting the potential on said corresponding reading bit line (4), and
• second activating means (9) for activating said switching means (8) during said predetermined time period and subsequent to said predetermined portion.

A serial access semiconductor memory device comprising:

• a plurality of memory cells (1) arranged in a matrix of rows ad columns;
• a writing word line (5) corresponding to each row of memory cells (1) and a writing bit line (3) corresponding to each column of memory cells (1) for selectively writing information to said memory cells (1);
• a reading word line (6) corresponding to each row of memory cells (1) and a reading bit line (4) corresponding to each column of memory cells (1) for selectively reading information from said memory cells (1),
• each memory cell (1) comprising a writing transistor (14), a storage capacitor (17), a storage transistor (15) and a reading transistor (16),
• selecting means (114) for sequentially selecting one of said reading bit lines (4) for a predetermined period,
• precharging means (7) corresponding to each of said reading bit lines (4) for precharging said corresponding reading bit lines (4) to a predetermined potential, and
• activating means (114) for activating one of said precharging means (7) corresponding to the selected read bit line only for said predetermined period.

A semiconductor memory device comprising:

• a plurality of memory cells (1) arranged in a plurality of columns,
• reading bit lines (4) provided corresponding to said plurality of columns,
• selecting means (9,114) for selecting one said reading bit lines (4), and
• precharging means (7) provided corresponding to said respective reading bit lines (4) for precharging, only for a predetermined period, a corresponding reading bit line (4) to a predetermined potential when said corresponding reading bit line (4) is selected by said selecting means (9, 114).