Semiconductor memory apparatus
AssigneeMatsushita Electronics Corporation
InventorMichiharu Shikata
Life of this patent
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Abstract
In a semiconductor memory apparatus having a plurality of sense amplifiers each including a pair of flip-flops respectively formed of n-channel and p-channel FETs, the flip-flops being connected in parallel between a pair of data lines each coupled to receive data signals from a plurality of memory cells, the p-channel flip-flops are activated prior to the n-channel flip-flops at the start of a memory read operation, to thereby ensure that even with an adverse combination of logic states of a data word read from a very large storage capacity memory, there will be no significant difference between the respective time points at which amplification by the n-channel flip-flop and p-channel flip-flops of each sense amplifier begin.
Claims1
A semiconductor memory apparatus comprising a plurality of sense amplifier circuits arrayed in parallel, each sense amplifier circuit including:
- first and second data lines respectively connected in parallel to a plurality of memory cells;
- a first flip-flop formed of first and second n-channel metal insulation semiconductor field effect transistors with the source electrodes thereof connected in common, with the gate electrodes and drain electrodes thereof mutually cross-coupled, and with the drain electrodes thereof respectively connected to the first and second data lines;
- a second flip-flop formed of first and second p-channel metal insulation semiconductor field effect transistors with the source electrodes thereof connected in common, the gate electrodes and drain electrodes thereof mutually cross-coupled, and with the drain electrodes thereof respectively connected to the first and second data lines, the source electrodes of the first flip-flops of the plurality of sense amplifier circuits being mutually connected as a first common connection node, and the source electrodes of the second flip-flops of the plurality of sense amplifier circuits being mutually connected as a second common connection node;
- a first switching transistor coupled between the second common connection node and a first potential of a power source;
- a second switching transistor coupled between the first common connection node and a second potential of the power source;
- a third switching transistor coupled between the second common connection node and the first potential of the power source;
- and
- operation timing means operable for initiating a read operation of the semiconductor memory apparatus, including means for consecutively setting the first switching transistor into a conducting condition at a first predetermined time point, the second switching transistor into a conducting condition at a second predetermined time point subsequent to the first time point, and the third switching transistor into a conducting condition at a third predetermined time point subsequent to the second time point.
Dependencies are inferred from the claim text.