Horizontal synchronizing signal generating circuit

A horizontal synchronizing signal generating apparatus comprising:

• horizontal synchronizing reference signal producing means for producing an internal horizontal synchronizing reference signal based upon an inputted clock signal and a reset pulse;
• masking signal generating means for generating a first masking signal which decides a first dead zone in the vicinity of a prescribed edge of the internal horizontal synchronizing reference signal, and a second masking signal which decides a second dead zone wider than the first dead zone;
• dead-zone changeover means for selecting either the first or second masking signal dependent upon a dead-zone changeover signal;
• reset-pulse generating means for generating a reset pulse synchronized to a prescribed edge, which corresponds to said prescribed edge of the internal horizontal synchronizing reference signal, of a given external horizontal synchronizing reference signal;
• and
• reset control means for determining whether the prescribed edge of the given external horizontal synchronizing reference signal lies within the first or second dead zone decided by the first or second masking signal selected by said dead-zone decided by the first or second masking signal selected by said dead-zone changeover means, and applying the reset pulse to said horizontal synchronizing reference signal producing means when the prescribed edge of the given external horizontal synchronizing reference signal fails to lie within the first or second dead zone selected by the dead-zone changeover means.

A synchronizing signal generating apparatus comprising:

• a voltage-controlled oscillator for generating a clock signal in conformity with a control voltage applied thereto, wherein the frequency of the clock signal becomes higher as the control voltage becomes higher;
• synchronizing signal producing means for producing an internal synchronizing signal by frequency-dividing the clock signal generated by said voltage-controlled oscillator, and generating said internal synchronizing signal, which begins from a prescribed edge of a given external synchronizing signal, when a reset signal synchronized to the prescribed edge is applied;
• an edge-detecting digital phase comparator for detecting, based on a comparison with the prescribed edge, a phase difference between the internal synchronizing signal outputted by said synchronizing signal producing means and the given external synchronizing signal, and for outputting a digital signal which represents the phase difference detected;
• a low-pass filter responsive to a change in the digital signal outputted by said edge-detecting digital phase comparator for generating a first control voltage when the phase of the internal synchronizing signal leads the phase of the external synchronizing signal, and a second control voltage lower than said first control voltage when the phase of the internal synchronizing signal lags behind the phase of the external synchronizing signal, and applying the first or second control voltage generated to said voltage-controlled oscillator;
• and
• forcible pull-in means for applying, to said voltage-controlled oscillator for a prescribed period of time immediately following introducing of power, a control voltage high enough to generate a clock signal whose frequency is higher than a central frequency of said voltage-controlled oscillator.

A synchronizing method of a synchronizing signal generating apparatus having a voltage-controlled oscillator for generating a click signal whose frequency varies in proportion with a control voltage applied thereto, synchronizing signal producing means for producing an internal synchronizing signal by frequency-dividing the clock signal provided by the voltage-controlled oscillator, and generating an internal synchronizing signal, which begins from a prescribed edge of a given external synchronizing signal, when a reset signal synchronized to the prescribed edge is applied, an edge-detecting digital phase comparator for detecting, based on a comparison with the prescribed edge, a phase difference between the internal synchronizing signal outputted by the synchronizing signal producing means and the given external synchronizing signal, and for outputting a digital signal which represents the phase difference detected, and a low-pass filter for generating a control voltage, which is to be applied to the voltage-controlled oscillator, whose lever varies in response to a change in the digital signal outputted by the edge-detecting digital phase comparator, said method comprising the steps of:

• applying, to said voltage-controlled oscillator at start-up of said synchronizing signal producing means, a control voltage whose level causes generation of a clock signal whose frequency is higher than a center frequency of said voltage-controlled oscillator;
• and
• synchronizing the internal synchronizing signal to the given external synchronizing signal in a process which causes the frequency of the clock signal to change from a first frequency to a second frequency lower than said first frequency.

A method for generating a horizontal synchronizing signal, comprising the steps of:

• (a) producing an internal horizontal synchronizing reference signal based upon an inputted clock signal and a reset pulse;
• (b) comparing the phase of a given external horizontal synchronizing reference signal and the phase of an internal horizontal synchronizing reference signal produced at said step (a);
• (c) generating a phase comparator voltage signal conforming to a difference between the phases of said given external horizontal synchronizing reference signal and said internal horizontal synchronizing reference signal;
• (d) passing low frequency components of said phase comparator voltage signal generated at said step (c) to develop a low-pass filter output voltage signal;
• (e) generating a clock signal applied to said step (a) by a voltage-controlled oscillator whose oscillation frequency is controlled by said low-pass filter output voltage signal;
• (f) determining whether the phase difference between the phases of said internal horizontal synchronizing reference signal and said given external horizontal synchronizing reference signal lies within a follow-up range in which follow-up is capable of being performed by said voltage-controlled oscillator;
• (g) generating a reset pulse synchronized to a prescribed edge of said given external horizontal synchronizing reference signal;
• (h) inhibiting input of said reset pulse at said step (a) when said phase difference is determined to lie within said follow-up range at said step (f);
• and
• (i) applying said reset signal at said step (a) when said phase difference is determined to lie outside said follow-up range at said step (f).

A method for generating a horizontal synchronizing signal, comprising the steps of:

• (a) producing an internal horizontal synchronizing reference signal based upon an inputted clock signal and a reset pulse;
• (b) generating a first masking signal which decides a first dead-zone in the vicinity of a prescribed edge of said internal horizontal synchronizing reference signal;
• (c) generating a second masking signal which decides a second dead-zone wider than said first dead-zone;
• (d) selecting either said first or second masking signal in response to a dead-zone changeover signal;
• (e) generating a reset pulse synchronized to a prescribed edge of a given external horizontal synchronizing reference signal, which corresponds to said prescribed edge of said internal horizontal synchronizing reference signal;
• (f) determining whether said prescribed edge of said given external horizontal synchronizing reference signal lies within said first or second dead-zone decided by said first or second masking signal selected at said step (d);
• and
• (g) applying said rest pulse at said step (a) when said prescribed edge of said given external horizontal synchronizing reference signal fails to lie within said first or second dead-zone selected at said step (d).

A method for generating a horizontal synchronizing signal, comprising the steps of:

• (a) generating a clock signal by a voltage-controlled oscillator in conformity with an applied control voltage so that the frequency of said clock signal becomes higher as said applied control voltage becomes higher;
• (b) producing an internal synchronizing signal by frequency-dividing said clock signal generated at said step (a);
• (c) generating said internal synchronizing signal from a prescribed edge of a given external synchronizing signal when a reset signal synchronized to said prescribed edge of said given external synchronizing signal is applied;
• (d) detecting a phase difference between said internal synchronizing signal generated at said step (c) and said given external synchronizing signal based on a comparison with said prescribed edge of said given external synchronizing signal;
• (e) outputting a digital signal which represents said phase difference detected at said step (d);
• (f) generating a first control voltage when the phase of said internal synchronizing signal leads the phase of said external synchronizing signal responsive to a change in said digital signal outputted at said step (e);
• (g) generating a second control voltage lower than said first control voltage when the phase of said internal synchronizing signal lags behind the phase of said external synchronizing signal;
• (h) applying said first control voltage generated at said step (f) or said second control voltage generated at said step (g) as said applied control voltage at said step (a);
• and
• (i) applying a clock control voltage to said voltage-controlled oscillator for a prescribed period of time immediately following introduction of power high enough to generate a clock signal whose frequency is higher than a central frequency of said voltage-controlled oscillator.

A synchronizing signal generating apparatus, comprising:

• a voltage-controlled oscillator for generating a clock signal whose frequency varies in proportion with a control voltage applied thereto;
• synchronizing signal producing means for producing an internal synchronizing signal by frequency-dividing said clock signal provided by said voltage-controlled oscillator and generating an internal synchronizing signal, which begins from a prescribed edge of a given external synchronizing signal, when a reset signal synchronized to said prescribed edge of said given external synchronizing signal is applied;
• an edge-detecting digital phase comparator for detecting a phase difference between said internal synchronizing signal outputted by said synchronizing signal producing means and said given external synchronizing signal based on a comparison with said prescribed edge of said given external synchronizing signal and outputting a digital signal which represents said phase difference detected;
• a low-pass filter for generating a control voltage, which is to be applied to said voltage-controlled oscillator, whose level varies in response to a change in said digital signal outputted by said edge-detecting digital phase comparator;
• control voltage applying means for applying, to said voltage-controlled oscillator at start-up of said synchronizing signal producing means, a control voltage whose level causes generation of a clock signal whose frequency is higher than a center frequency of said voltage-controlled oscillator;
• and
• synchronizing means for synchronizing said internal synchronizing signal to said given external synchronizing signal to a process which causes the frequency of said clock signal to change from a first frequency to a second frequency lower than said first frequency.