Circuit for limiting maximum frequency output of a voltage controlled oscillator

A circuit comprising:

• a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency, wherein said VCO is connected within a phase-locked loop (PLL);
• a first circuit connected to an output of said VCO and having a maximum operating frequency above which said first circuit no longer accurately performs, said VCO being capable of generating an output signal having an output frequency which exceeds said maximum operating frequency of said first circuit;
• and
• means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit being chosen based upon said maximum operating frequency of said first circuit.

The circuit comprising:

• a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency;
• means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit not being based upon a reference clock frequency, wherein said VCO is connected within a phase-locked loop (PLL) and wherein said means for decreasing said output frequency comprises:
• a first input terminal connected to receive a first signal corresponding to said frequency of said VCO output signal;
• a first comparator means for comparing said first signal to a first reference signal and outputting at a first comparator output terminal a decrease frequency signal if said first comparator means detects that said frequency of said VCO output signal is greater than a level corresponding to said first reference signal,
• said decrease frequency signal outputted by said comparator means causing said frequency of said VCO output signal to fall;
• a second comparator means for comparing said first signal to a second reference signal and outputting at a second comparator output terminal a second signal indicating that said frequency of said VCO output signal is below a certain frequency, said second signal causing said frequency of said VCO output signal to not be further lowered by an output of said first comparator,
• wherein said decrease frequency signal is applied to a latch to set said latch, and said second signal is applied to said latch to reset said latch, an output of said latch being connected to control said frequency of said VCO output signal in response to a set condition of said latch.

A circuit comprising:

• a voltage controlled oscillator (VCO), said VCO generating an output signal having an output frequency;
• means for decreasing said output frequency if said frequency exceeds a preset limit, said preset limit not being based upon a reference clock frequency, wherein said means for decreasing said output frequency comprises:
• a first input terminal connected to receive a first signal corresponding to said frequency of said VCO output signal;
• a first comparator means for comparing said first signal to a first reference signal and outputting at a first comparator output terminal a decrease frequency signal if said first comparator means detects that said frequency of said VCO output signal is greater than a level corresponding to said first reference signal,
• said decrease frequency signal outputted by said first comparator means being applied to a first input terminal of a logic gate means, a second input terminal of said logic gate means being connected to a first output terminal of a phase/frequency detector for detecting a difference in phase/frequency between a reference clock signal and a signal corresponding to said frequency of said VCO output signal, a signal of a first logic level applied to said first or second input terminal of said logic gate means causing said logic gate means to output a signal to lower said VCO output frequency,
• an output terminal of said logic gate means being connected to an input of a voltage generating means for changing a level of a VCO control signal, so that when said decrease frequency signal is generated by said first comparator means, said VCO control signal will change to lower said frequency of said VCO output signal,
• wherein, when said first comparator means does not generate said decrease frequency signal, said logic gate means is transparent to an operation of said phase/frequency detector and said VCO.