Method of fabricating programmable read only memory device having trench isolation structure
AssigneeNEC Corporation
InventorTakeshi Okazawa
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AssigneeNEC Corporation
InventorTakeshi Okazawa
Estimating the term…
A method of fabricating a semiconductor integrated circuit comprises the steps of selectively forming a first gate insulating film on a main surface of a semiconductor substrate. Thereafter, the following layers are formed in sequence on the substrate: a first polysilicon layer, a second gate insulating film, and a second polysilicon layer. Then, insulating trenches are formed by selectively removing the second polysilicon layer, the second gate insulating film, the first polysilicon layer, the first gate insulating film, and the semiconductor substrate. Thereafter, a BPSG film is formed over the entire surface, filling the trenches. Selectively removing the BPSG film to leave it only in the trenches. Heretofore, the phosphorus and boron contained in the BPSG evaporated in response to a heat treatment used for forming the gate SiO.sub.2 film. Therefore, a portion of the evaporated phosphorus or boron was taken into the gate SiO.sub.2 film which degraded the characteristics and the reliability of each PROM cell transistor. The invention grows the BPSG film after the first and second gate insulating film is formed. Hence phosphorus or boron contained in the BPSG film is not taken into both of the gate insulating films.
A method of fabricating a semiconductor integrated circuit device, comprising the steps of:
A method of fabricating a semiconductor integrated circuit, comprising the steps of:
A method of fabricating a semiconductor integrated circuit, comprising the steps of:
A method of fabricating a semiconductor device having a plurality of PROM cell transistors, comprising the steps of selectively forming on a semiconductor substrate a first gate insulating film for each of said PROM cell transistors, forming on said first gate insulating film a first polysilicon layer operating as a floating gate for each of said PROM cell transistors, forming on said first polysilicon layer a second gate insulating film for each of said PROM cell transistors, forming on said second gate insulating film a second polysilicon layer operating as a control gate for each of said PROM cell transistors, selectively removing said second polysilicon layer, said second gate insulating film, said first polysilicon layer, said first gate insulating film and said semiconductor substrates to form trenches for isolating said PROM cell transistors from one another, filling said trenches with a borophosphosilicate glass layer, and selectively etching said second polysilicon layer, said second gate insulating film and said first polysilicon layer to form the control gate, the floating gate, the second gate insulating film between the control and floating gates and the first gate insulating film between the floating gate and said semiconductor substrate for the respective ones of said PROM cell transistors.
A method of providing electrical isolation between devices on a semiconductor substrate, said method comprising the steps of;
Dependencies are inferred from the claim text.