Manufacturing a semiconductor integrated circuit device having on chip logic correction

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

• providing a semiconductor wafer having semiconductor elements arranged in chip regions of the semiconductor wafer;
• forming primary wiring to interconnect the semiconductor elements, so as to form a plurality of macrocells in at least one of the chip regions;
• removing at least one of the macrocells of the plurality of macrocells, thereby forming a respective macrocell removed region for each removed macrocell;
• replacing said at least one of the macrocells, at the respective macrocell removed region, with a different macrocell, said different macrocell having a different circuit function than said at least one of the macrocells, said different macrocell being positioned at said respective macrocell removed region;
• and
• forming secondary wiring to interconnect the different macrocell and remaining ones of the plurality of macrocells.

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

• forming predetermined semiconductor integrated circuit elements in a chip region on a semiconductor wafer;
• arranging a plurality of macrocells having the same circuit function regularly in said chip region by a primary wiring process;
• arranging, regularly in each of the plurality of macrocells, test pads which are connected to a main circuit portion in the macrocell through a shift register circuit portion formed in the interior of the macrocell;
• after arranging the test pads, converting check data which have been inputted in series through said test pads into parallel signals through the shift register circuit portion and inputting the parallel signals to the main circuit portion, so as to check electrical characteristics of each macrocell in the chip region;
• converting detection data which have been outputted in parallel from the main circuit portion in accordance with said check data into serial signals through the shift register circuit portion and outputting the serial signals to the test pads;
• comparing the detection data outputted to the test pads with an expected value to provide a judgment whether the macrocell is good or defective;
• preparing macrocell quality information on the basis of results of said judgment;
• removing a defective macrocell from the semiconductor wafer, on the basis of said macrocell quality information, thereby forming a defective macrocell removed region, the defective macrocell removed region not extending an entire thickness of the semiconductor wafer;
• after removing a defective macrocell, embedding a good macrocell in the defective macrocell removed region;
• and
• interconnecting the macrocells in the chip region by a secondary wiring process to form a predetermined semiconductor integrated circuit in the chip region.

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

• forming predetermined semiconductor integrated circuit elements in a chip region on a semiconductor wafer;
• arranging a plurality of macrocells having the same circuit function regularly in said chip region by a primary wiring process;
• forming, regularly in each of said plurality of macrocells, test pads which are connected to a main circuit portion in the macrocell through a shift register circuit portion formed in the interior of the macrocell;
• after forming the test pads, converting check data which have been inputted in series through said test pads into parallel signals through the shift register circuit portion and inputting the parallel signals to the main circuit portion, so as to check electrical characteristics of the macrocells in the chip region;
• converting detection data which have been outputted in parallel from the main circuit portion in accordance with said check data into serial signals through the shift register circuit portion and outputting the serial signals to the test pads;
• preparing macrocell information on the basis of the outputted detection data;
• removing a defective macrocell on the basis of said macrocell information, to thereby form a macrocell removed region;
• embedding a macrocell having a different circuit function than a circuit function of the defective macrocell in the macrocell removed region;
• and
• interconnecting the macrocells in the chip region by a secondary wiring process to form a predetermined semiconductor integrated circuit in the chip region.

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

• providing a semiconductor wafer having semiconductor elements arranged in chip regions of the semiconductor wafer;
• forming primary wiring to interconnect the semiconductor elements, so as to form a plurality of macrocells in at least one of the chip regions;
• without prior interconnecting the plurality of macrocells, testing electrical characteristics of the macrocells to determine whether any macrocells are defective;
• removing any defective macrocells, by forming a first trench surrounding defective macrocells and extending from an upper surface of the semiconductor wafer but not through an entire thickness of the wafer, and forming a second trench extending from a surface of the wafer opposed to the upper surface, so as to meet the first trench such that the defective macrocells can be removed from the semiconductor wafer;
• and
• after testing the macrocells to determine whether any macrocells are defective, forming secondary wiring to interconnect at least two of the plurality of macrocells with each other.

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

• forming predetermined semiconductor integrated circuit elements in a chip region on a semiconductor wafer;
• arranging a plurality of macrocells having the same circuit function regularly in said chip region by a primary wiring process;
• arranging, regularly in each of the plurality of macrocells, test pads which are connected to a main circuit portion in the macrocell through a shift register circuit portion formed in the interior of the macrocell;
• after arranging the test pads, converting check data which have been inputted in series through said test pads into parallel signals through the shift register circuit portion and inputting the parallel signals to the main circuit portion, so as to check electrical characteristics of each macrocell in the chip region;
• converting detection data which have been outputted in parallel from the main circuit portion in accordance with said check data into serial signals through the shift register circuit portion and outputting the serial signals to the test pads;
• comparing the detection data outputted to the test pads with an expected value to provide a judgment whether the macrocell is good or defective;
• preparing macrocell quality information on the basis of results of said judgment;
• removing a defective macrocell on the basis of said macrocell quality information, thereby forming a defective macrocell removed region, the step of removing the defective macrocell including sub-steps of forming a first trench surrounding defective macrocells and extending from an upper surface of the semiconductor wafer but not through an entire thickness of the wafer, and forming a second trench extending from a surface of the wafer opposed to said upper surface, so as to meet the first trench such that the defective macrocells can be removed from the semiconductor wafer;
• after removing a defective macrocell, embedding a good macrocell in the defective macrocell removed region;
• and
• interconnecting the macrocells in the chip region by a secondary wiring process to form a predetermined semiconductor integrated circuit in the chip region.

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

• providing a semiconductor wafer having semiconductor elements arranged in chip regions of the semiconductor wafer, the semiconductor wafer having a thickness;
• forming primary wiring to interconnect the semiconductor elements, so as to form a plurality of macrocells in at least one of the chip regions;
• removing semiconductor elements from a region of the semiconductor wafer so as to form a macrocell removed region, the macrocell removed region not extending the thickness of the semiconductor wafer;
• and
• thereafter, forming secondary wiring to interconnect at least two of the plurality of macrocells with each other.