Method for forming a raised vertical transistor

A method for forming a transistor comprising the steps of:

• providing a silicon substrate having a surface and being of a first conductivity type;
• forming a first dielectric layer overlying the silicon substrate;
• depositing a control electrode polysilicon layer overlying the first dielectric layer;
• depositing a second dielectric layer overlying the control electrode polysilicon layer;
• sequentially removing portions of each of the second dielectric layer, the control electrode polysilicon layer, and the first dielectric layer, the sequential removing forming an opening which exposes the surface of the silicon substrate and forming a sidewall of the control electrode polysilicon layer;
• etching the sidewall of the control electrode polysilicon layer to laterally recess the sidewall of the control electrode polysilicon layer;
• growing a sidewall oxide laterally adjacent the sidewall of the control electrode polysilicon layer, the sidewall oxide functioning as a gate dielectric;
• and
• growing an epitaxial region within the opening, the epitaxial region having a first portion of a second conductivity type which functions as a first current electrode, the first portion being laterally adjacent the first dielectric layer and overlying the silicon substrate, the epitaxial region having a second portion of the first conductivity type functioning as a channel region, the second portion being laterally adjacent the sidewall oxide, and overlying the first current electrode, and the epitaxial region having a third portion of the second conductivity type functioning as a second current electrode, the third portion being laterally adjacent the second dielectric layer and overlying the channel region.

A method for forming a vertical field effect transistor comprising the steps of:

• providing a substrate having a surface and being of a first conductivity type;
• forming a first dielectric layer overlying the substrate;
• forming a control electrode conductive layer overlying the first dielectric layer;
• forming a second dielectric layer overlying the control electrode conductive layer;
• removing portions of each of the first dielectric layer, the control electrode conductive layer, and the second dielectric layer to form both an opening which exposes the surface of the substrate and a sidewall of the control electrode conductive layer;
• laterally recessing the sidewall of the control electrode conductive layer;
• growing a sidewall dielectric laterally adjacent the sidewall of the control electrode conductive layer;
• growing a first conductive region within the opening, the first conductive region being of a second conductivity type and functioning as a first current electrode, the first conductive region being laterally adjacent the first dielectric layer and overlying the substrate;
• growing a second conductive region within the opening, the second conductive region being of the first conductivity type and functioning as a channel region, the second conductive region being laterally adjacent the sidewall dielectric and overlying the first current electrode;
• and
• growing a third conductive region within the opening, the third conductive region being of the second conductivity type and functioning as a second current electrode, the third conductive region being laterally adjacent the second dielectric layer and overlying the channel region.