Process for preparing BiCMOS semiconductor device
AssigneeSharp Kabushiki Kaisha
InventorToshinori Ohmi
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Abstract
A process for preparing a BiCMOS semiconductor device having a MOS transistor element and a bipolar transistor element both of which are constituted in an epitaxial layer of n-type conductivity formed on a substrate of p-type conductivity, which comprises applying, after the formation of said epitaxial layer, an impurity ion of high energy simultaneously to specific of said epitaxial layer under which a channel region of said MOS transistor element and an emitter region of said bipolar transistor element are to be formed, thereby forming highly doped impurity regions around the bottom of said channel region and around the bottom of a base region of said bipolar transistor element.
Claims2
A process for preparing a BiCOMOS semiconductor device having a MOS transistor element and a vertical type bipolar transistor element, said elements both being constituted in an epitaxial layer of n-type conductivity formed on a substrate of p-type conductivity, said process comprising the step of:
- (i) implanting n-type impurities at a high energy simultaneously around the bottom of a channel region of the p-channel MOS transistor and around the bottom of the base region of the NPN transistor.
- (ii) implanting p-type impurities at a high energy simultaneously around the bottom of a channel region of the n-channel MOS transistor and around the bottom of the base region of PNP-transistor, thereby forming a highly-doped impurity region having an impurity type opposite to the source-drain region around the bottom of said channel region of said MOS transistor element as well as a highly-doped impurity region having an impurity type opposite to the base region around the bottom of said base region of said bipolar transistor element.
Dependencies are inferred from the claim text.