US 5,208,169 A · Method of forming high voltage bipolar transistor for a BICMOS integrated circuit

Abstract

A high voltage bipolar transistor (10) is fabricated in an N- HV/epitaxial well (12) formed by an N- substrate implant and the overlying portion of the N- epitaxial layer 12b. The N- substrate implant replaces the normal buried N+ collector layer, in effect extending the depth of the epitaxial layer to increase junction breakdown voltages. The collector is formed by buried N+ collector regions (14a and 14b) formed adjacent to, and on either side of, the N- substrate implant. The transistor is fabricated conventionally in the N- HV/epitaxial well, except that, to further enhance high voltage performance, P+ extrinsic base regions (23a and 23b) can be extended using optional deep P+ implants (reducing curvature effects which correspondingly reduces electric field, and thereby inhibits premature junction breakdown).

Claims12

Dependent claims

An HV BICMOS method of fabricating relatively high voltage (HV) bipolar transistors in a BICMOS integrated circuit using a semiconductor substrate of a first conductivity type over which is formed an epitaxial layer of a second conductivity type, comprising the steps:

forming in each of selected number of HV regions in the substrate an HV well of the second conductivity type with a dopant concentration about the same as the epitaxial layer;
forming adjacent to each HV well at least one collector region of the second conductivity type with a dopant concentration substantially greater than the epitaxial layer;
forming the epitaxial layer over the substrate including each HV well, thereby forming an HV/epitaxial well;
over each collector region, forming in the epitaxial layer a collector contact region extending through the epitaxial layer to the collector region;
in each epitaxial/HV well, forming a base region of the first conductivity type, insulated from the collector contact region;
and
forming an emitter of the second conductivity type over the base region.

4 more elements

An HV/LV BICMOS method of fabricating a BICMOS integrated circuit that includes relatively high voltage (HV) and relatively low voltage (LV) bipolar transistors, which uses a semiconductor substrate of a first conductivity type over which is formed an epitaxial layer of a second conductivity type, comprising the steps:

forming in each of selected number of HV regions in the substrate an HV well of the second conductivity type with a dopant concentration about the same as the epitaxial layer;
forming adjacent to each well at least one HV collector region, and forming in each of a selected number of LV regions in the substrate an LV collector region, the HV and LV collector regions being of the second conductivity type with a dopant concentration substantially greater than the epitaxial layer;
forming the epitaxial layer over the substrate including each HV well, thereby forming an HV/epitaxial well;
in a portion of each HV and LV collector region, forming in the epitaxial layer a collector contact region of the second conductivity type extending through the epitaxial layer to the collector region;
in each HV/epitaxial well and over each LV collector region, forming a base region of the first conductivity type, insulated from the collector contact region;
and
forming an emitter of the second conductivity type over the base region.

4 more elements

Dependencies are inferred from the claim text.

Method of forming high voltage bipolar transistor for a BICMOS integrated circuit

Life of this patent

Method of forming high voltage bipolar transistor for a BICMOS integrated circuit

Life of this patent

Abstract

Claims12