Fast store-through cache memory

In a system for processing and storing bit-encoded data including data words, each data word having a plurality of data bits, the system including a processing device for manipulating bit-encoded data, a main storage memory having arrays for storing bit-encoded data as data words, a main storage interface connected to the processing device and to the main storage memory for transmitting bit-encoded data between the processing device and the main storage memory;

• said processing device having an associated store-through cache memory and associated processor logic for gaining access to cache locations within the cache memory and for accessing memory locations in the main storage memory to store and retrieve bit-encoded data;
• the cache memory including a plurality of cache locations each corresponding to a memory location in the main storage memory, and a cache directory for indicating the memory locations resident as corresponding cache locations in the cache memory and for alternatively indicating a valid condition or an invalid condition of each cache location;
• and
• a timing means for generating a timing signal including timing pulses at a constant frequency, and for providing the timing signal to said processing device;
• a process for storing data including the steps of:
• during a first clock cycle, storing a first data word to a first cache location in the cache memory, and reading a cache directory of the cache memory to determine the presence or absence of a need to modify the cache directory in view of storing the first data word;
• storing the first data word to a first memory location in the main storage memory;
• during a second clock cycle immediately following the first clock cycle, and responsive to determining the need to modify the cache directory, generating a first interrupt signal for interrupting the processing device associated with the cache memory during a third clock cycle to free the associated cache memory interface during the third clock cycle;
• and
• modifying the cache directory during the third clock cycle.

A network for processing bit-encoded data, including:

• at least one processing device for manipulating bit-encoded data as data words, each data word having a plurality of data bits;
• a main storage memory having a plurality of memory locations for storing bit-encoded data as data words, and a main storage interface connected to the processing device and to the main storage memory for transmitting bit-encoded data between the processing device and the main storage memory;
• wherein said processing device includes a store-through cache memory having a plurality of cache locations, each cache location corresponding to one of the memory locations in the main storage memory, and a cache interface associated with the cache memory, said cache memory further including a cache directory for identifying the memory locations resident as corresponding cache locations in the cache memory, and for indicating alternative valid and invalid conditions for each of the cache locations;
• a timing means for generating a timing signal including timing pulses at a constant frequency to provide clock cycles of uniform duration, the timing means being operably connected to the processor and providing the timing signal to the processing device;
• and
• logic circuitry operably associated with said processing device, including circuitry for storing a first data word to a first cache location via the cache interface and circuitry for reading the cache directory for a need to modify the cache directory in view of storing the first data word during a first cycle of three consecutive ones of said clock cycles;
• circuitry responsive to determining the need to modify the cache directory in view of storing the first data word, for generating a first interrupt signal for interrupting the processing device to free the cache memory interface and circuitry for storing the first data word to a first memory location in the main storage memory, during a second consecutive clock cycle;
• and circuitry for interrupting the processing device and modifying the cache directory in view of storing the first data word, during a third consecutive clock cycle.