Address control and generating system for digital signal-processor

An address generating system for a digital signal processor having an instruction memory which stores microinstructions indicating arithmetic or logical operations and data address control operations, a data memory which stores data, an execution unit which executes arithmetic or logical operations on data read from said data memory according to said microinstructions, and a data bus for transferring data among components of said digital signal processor including said data memory, said execution unit, and said address generating system, said address generating system comprising:

• at least one address generator which independently generates, according to said microinstructions, read addresses for reading data from said data memory to be inputted to said execution unit as input data, and write addresses for writing data outputted from said execution unit into said data memory, said address generator including
• at least one address register for storing an initial address value inputted from said data bus and at least one index register for storing an address modification value inputted from said data bus, said stored initial address value and said stored address modification value also being outputtable to said data bus,
• means for respectively selecting said at least one address register and said at least one index register according to said microinstructions,
• means for calculating output address data according to said microinstructions, including means for selectively adding together contents of said selected address register, contents of said selected index register as a relative index value, and displacement data as a relative modification value indicated by said microinstructions, in accordance with said microinstructions, and
• means for updating the contents of said selected address register with said calculated output address data;
• wherein an address for a first reference point of an object data series is designated as the content of a selected address register, addresses for subsequent reference points are designated by said means for calculating based on said microinstructions, and continuous addresses for irregularly arranged data series are designated by sequential repetition of processing by said means for calculating and said means for updating in accordance with said microinstructions.