Apparatus and method for fast I/O data transfer in an intelligent cell

In a network including a plurality of intelligent cells, each cell comprising a central processing unit and a random-access memory (RAM), said RAM being coupled to an input/output (I/O) module across an internal bus, a method of transferring multiple bytes of data to said memory from said module across said internal bus, said method executed by said CPU and comprising the steps of:

• (a) programming said I/O module to initiate a data transfer from an external device;
• (b) storing a current RAM address into a first register and a current count, representing the remaining number of bytes to be transferred across said internal bus, into a second register;
• (c) checking said I/O module to determine if a data byte is available from said external device, if said data byte is available, said CPU instructing said I/O module to place said data byte on said internal bus for storage within said RAM at said current RAM address, if said data byte is unavailable, said CPU waiting until said data byte is available;
• (d) incrementing said current RAM address and storing the incremented address back in said first register;
• (e) decrementing said current count and storing the decremented count back in said second register;
• (f) determining whether said current count equals a predetermined number:
• (g) repeating steps (c)-(f) until said count equals said predetermined number.

An apparatus having a central processing unit (CPU), a random-access memory (RAM) and an input/output (I/O) means for exchanging information between said processor and an external device, said I/O means being coupled to said RAM across an internal bus, a processor executable instruction for instructing said CPU to transfer multiple bytes of data between said RAM and said I/O means, wherein said instruction involves a plurality of clock cycles for said CPU to complete said transfer before a following instruction is to be executed by said CPU, comprising:

• register means of storing a current address location for data to be transferred from/to said RAM to/from said I/O means, said register means also storing the current count of the number of data bytes yet to be transferred across said internal bus;
• control means operative within said CPU for successively transferring an available byte of data to/from said I/O means from/to said current address location in said RAM via said internal bus, said control means providing a signal following each transfer;
• logic means operative within said CPU for responding to said signal by incrementing said current address and decrementing said current count, wherein the incremented address and decremented count are stored in said register means as said current address and said current count, respectively, prior to the transfer of the next available byte of data, said logic means including a means for terminating said transfer whenever said current count equals a predetermined number.