Data link controller with channels selectively allocatable to hyper channels and hyper channel data funneled through reference logical channels

In a communication controller for interfacing between a data processing system and a signal communication network, said controller having a plurality of internal channels selectively allocatable for interfacing to discrete external communication channels in said network, each of said internal channels having reserved exclusively thereto internal buffer memory for temporary storage of data signals being transferred between it and said network, an arrangement for operating a selected group of plural internal channels, in time coordination, as an extended bandwidth logical internal channel, in order to interface with an external channel on said network which operates at data signal transmission rates exceeding the capacity of a single said internal channel, said arrangement comprising:

• random access memory (RAM) means having storage spaces therein reserved to individual said internal channels;
• first means coupled to said RAM means for assigning a group of selected ones of said internal channels as constituents of a said extended bandwidth logical internal channel;
• said first means including means for designating a selected one of said assigned internal channels as a reference channel for the respective group;
• second means coupled to said first means for defining operations to be conducted between all of said assigned internal channels and a single associated external channel;
• and
• third means, coupled to said first and second means, for conducting data transfer operations, in time coordination, between said associated external channel and each of said assigned internal channels;
• said third means including means for effectively transferring data signals in transit relative to said associated external channel between each said assigned internal channel and only storage space in said RAM reserved to said reference channel;
• whereby all data in transit between the associated external channel served by each said group and said data processing system is effectively funneled through only the internal buffer storage space reserved to said reference channel;
• and wherein:
• said internal channels are served in cyclically recurrent time slots of cyclically recurrent time frames;
• each internal channel having a time slot position in each said frame uniquely assigned thereto;
• said controller includes means for generating numerical slot indications in synchronism with occurrences of said time slots, said indications representing time positions of respectively occurring slots in said frame;
• and
• said third means includes for selectively translating each said slot position assigned to an internal channel in said group other than said reference channel into the slot position indication assigned to said reference channel;
• whereby data transfer operations relative to said RAM during each time slot allocated to the internal channels in said groups are steered to a space in said RAM dedicated to the respective reference channel of the group.