Counter circuit with direction of count indication
AssigneeFujitsu Limited
InventorAtsushi Fujita
Life of this patent
Estimating the term…
Abstract
A counter circuit comprises a signal detector for providing an up/down indication signal and a count clock signal according to an up/down signal and a reference clock signal. A n-bit counter for providing up/down count data of "n" bits according to the up/down indication signal and count clock signal. A counting direction detector provides a counting direction signal according to the up/down indication signal and reference clock signal. This counter circuit itself determines whether it is counting up or counting down, by hardware, and thus can instantaneously respond to a direction identification request from a central processing unit.
Claims12
A counter circuit comprising:
- a signal detector means for providing an up/down indication signal and a count clock signal according to an up/down signal and a reference clock signal input thereto;
- an n-bit counter means, connected to said signal detector means, for providing up/down count data of "n" bits according to the up/down indication signal and count clock signal;
- and
- a counting direction detector means, connected to said signal detector means and said reference clock signal input, for providing a counting direction signal according to the up/down indication signal and reference clock signal.
A counter circuit comprising:
- a signal detector means for providing an up/down indication signal and a count clock signal according to an up/down signal and a reference clock signal;
- an n-bit counter means for providing up/down count data of "n" bits according to the up/down indication signal and count clock signal;
- and
- a counting direction detector means for providing a counting direction signal according to the up/down indication signal and reference clock signal, said counting direction detector includes
- a first signal generator for providing a first set signal and a first reset signal in response to the up/down indication signal and reference clock signal,
- a first data holding means for receiving the first set signal and first reset signal and providing an up direction signal,
- a second signal generator for providing a second set signal and a second reset signal in response to the up/down indication signal and reference clock signal, and
- a second data holding means for receiving the second set signal and second reset signal and providing a down direction signal.
Dependencies are inferred from the claim text.