Timing interpolator
AssigneeHewlett-Packard Company
InventorMark A. Unkrich
Life of this patent
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Abstract
A timing interpolator providing high resolution timing measurement of when an event occurs. The interpolator of the present invention includes three embodiments. The interpolator of the first embodiment includes a Voltage Controlled Oscillator (VCO) phase-locked loop, an N-bit counter, and an N-bit latch. The interpolator of the second embodiment includes a delay line phase-lock loop and an X-bit latch. The delay line phase-lock loop includes an X-bit delay cell chain and a phase detector. The interpolator of the third embodiment of the present invention represents a combination of the interpolators of the first and second embodiments. The interpolator of the third embodiment includes a VCO phase-locked loop, a delay line phase-lock loop and X-bit latches.
Claims18
An apparatus for timing an event, comprising:
- a phase-locked loop for producing a high frequency signal phase-locked to a low frequency signal;
- an N-bit counter for counting edges of the high frequency signal to produce a count value, wherein the N-bit counter comprises means for generating a least significant bit of the count value;
- a phase detector, coupled to the N-bit counter, for generating an output signal proportional to a phase difference between the low frequency signal and the least significant bit;
- a voltage controlled oscillator, coupled to the phase detector, for producing the high frequency signal from the output signal;
- and
- an N-bit latch for latching the count value from the N-bit counter upon receiving the event.
An apparatus for timing an event, comprising:
- a delay line phase-lock loop for phase locking a high frequency reference signal with a delayed high frequency signal, the delay line phase lock loop comprising means for generating multiple phases of the delayed high frequency signal;
- and
- an X-bit latch, coupled to said delay line phase-lock loop, for latching a state of each phase of the delayed high frequency signal upon receiving the event.
An apparatus for timing an event, comprising:
- a voltage controlled oscillator phase-locked loop for producing a high frequency signal in phase with a low frequency signal;
- a delay line phase-lock loop comprising:
- an X-bit delay cell chain for producing a delayed high frequency signal by delaying the high frequency signal;
- means for generating multiple phases of the delayed high frequency signal;
- and means for phase locking the high frequency signal with the delayed high frequency signal;
- and
- at least one X-bit latch, coupled to the delay line phase-lock loop, for latching a state of each phase of the delayed high frequency signal upon receiving the event.
An apparatus for timing an event, comprising:
- a phase-locked loop for producing a high frequency signal phase-locked to a low frequency signal, the phase-locked loop having an N-bit counter for counting edges of the high frequency signal to produce a count value;
- an N-bit latch, coupled to the N-bit counter, for latching the count value from the N-bit counter upon receiving the event;
- and
- a synchronizer, coupled to the N-bit counter and the phase-locked loop, for synchronizing the event with the high frequency signal to produce a synchronized event.
Dependencies are inferred from the claim text.