Error detection and correction memory system

A method of detecting and correcting errors in a memory system having first and second memory arrays, each memory array having a plurality of memory devices, said method comprising the steps of:

• storing a data work and a correction word in said memory devices, said data and correction words each having a first portion stored in said first memory array and a second portion stored in said second memory array;
• retrieving said data and correction words from said memory arrays;
• transmitting said data word from a first portion of each of said plurality of memory devices of said first array to a first error detecting and correcting means for detecting errors in said data word;
• transmitting said data word from a second portion of each of said plurality of memory devices of said first array to a second error detecting and correcting means for detecting errors in said data word,
• transmitting said data word from a first portion of each of said plurality of memory devices of said second array to said first error detecting and correcting means, and
• transmitting said data word from a second portion of each of said plurality of memory devices of said second array to said second error detecting and correcting means;
• checking said data word for an error;
• and
• correcting said error if one is found in said data word.

A method of detecting errors in a memory system having first and second memory arrays, each memory array having a plurality of memory devices, each memory device having a plurality of outputs, each of said plurality of outputs being coupled to a plurality of memory cells, said method comprising the steps of:

• storing a first portion of a first data word in said plurality of memory cells coupled to a first output of said plurality of outputs of said memory devices of said first memory array;
• storing a second portion of said first data word in said plurality of memory cells coupled to a first output of said plurality of outputs of said memory devices of said second memory array;
• storing a first portion of a second data word in said plurality of memory cells coupled to a second output of said plurality of outputs of said memory devices of said first memory array;
• storing a second portion of said second data word in said plurality of memory cells coupled to a second output of said plurality of outputs of said memory devices of said second memory array;
• storing a first portion of a first correction word in said plurality of memory cells coupled to a first output of said plurality of outputs of said memory devices of said first memory array;
• storing a second portion of said first correction word in said plurality of memory cells coupled to a first output of said plurality of outputs of said memory devices of said second memory array;
• storing a first portion of a second correction word in said plurality of memory cells coupled to a second output of said plurality of outputs of said memory devices of said first memory array;
• storing a second portion of said second correction word in said plurality of memory cells coupled to a second output of said plurality of outputs of said memory devices of said second memory array;
• retrieving said data and correction words from said memory arrays;
• transmitting said first portions of said first data and correction words to a first error detecting and correcting means for detecting errors;
• transmitting said second portions of said first data and correction words to a second error detecting and correcting means for detecting errors;
• transmitting said first portions of said second data and correction words to said second error detecting and correcting means;
• transmitting said second portions of said second data and correction words to said first error detecting and correcting means;
• combining said first portion of said first correction word and said second portion of said second correction word in said first error detecting and correcting means to check a first combination word comprised of said first portion of said first data word and said second portion of said second data word;
• combining said second portion of said first correction word and said first portion of said second correction word in said second error detecting and correcting means to check a second combination word comprised of said second portion of said first data word and said first portion of said second data word;
• checking said first and second combination words for an error;
• and
• correcting said error if one is found in said first or second data words.

An error detection memory system comprising:

• a first memory array having a plurality of memory devices, each of said plurality of memory devices having first and second outputs;
• a second memory array having a plurality of memory devices, each of said plurality of memory devices having first and second outputs;
• first error detecting and correcting means for detecting errors in a data word stored in said error detection memory system, said first error detecting and correcting means being coupled to said first outputs of said plurality of memory devices of said first memory array and to said second outputs of said plurality of memory devices of said second memory array;
• and
• second error detecting and correcting means for detecting errors in a data word stored in said error detection memory system, said second error detecting and correcting means being coupled to said second outputs of said plurality of memory devices of said first memory array and to said first outputs of said plurality of memory devices of said second memory array.