Method and apparatus for locally deriving test signals from previous response signals
AssigneeCrossCheck Technology, Inc.
InventorsSusheel J. Chandra, Tushar Gheewala
Life of this patent
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AssigneeCrossCheck Technology, Inc.
InventorsSusheel J. Chandra, Tushar Gheewala
Estimating the term…
An IC has local test circuitry including a test point array, instruction register, data register, probe line drivers and control/sense line drivers/receivers. To test the IC, the instruction register is loaded initiating the test circuitry to address select test points to receive control signals and to address other select test points at which response signals are to be sensed. Control signals are produced from the data register contents. The data register contents are derived as a function of the prior contents of the data register and a bit pattern formed from response signals of select test points. According to one embodiment, the prior contents are exclusively or'ed with the bit pattern of response signals to derive the new data register contents. A continuous test is performed by using prior response signals exclusively OR'ed to data register contents so as to generate subsequent control signals. Predesigned test sequences enable fast continuous testing of the IC.
A method for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the method comprising the steps of:
A method for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the method comprising the steps of:
An apparatus for defining a test signal for an IC test point based upon a logic state of a signal path local to the IC, the IC having an integral test structure comprising a plurality of probe lines, a plurality of control/sense lines and a data register, said data register for storing a first data pattern, the apparatus comprising:
Dependencies are inferred from the claim text.