US 5,206,861 AGranted

System timing analysis by self-timing logic and clock paths

AssigneeInternational Business Machines Corporation

InventorsNicholas P. Hannon, Albert Tarolli, Paul L. Wiltgen

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Abstract

A system and method of determining the propagation delay between LSSD (Level Sensitive Scan Delay) latch pairs is performed by modifying system and scan clock sequences. A set bit is initially scanned to the input of the sending trigger. This is done by inhibiting the last B clock. These A and B clocks are then gated off and the system clocks operate a complete cycle with the unique sequence of inhibiting the first latch pulse and the last trigger pulse. Finally, a unique scan clock sequence is used to scan out data from the receiving latch. If the data scanned out corresponds with expected data (the set bit), the process is repeated decreasing the cycle time of the system clocks until the set bit is no longer received. The measured delay is then taken as the preceding cycle time. By measuring the delays between a plurality of points and a common originating point and taking the differences in these delays, the skew in a clock distribution system can be readily determined.

Claims12

Dependent claims

In a system having level sensitive scan delay latch pairs composed of a latch and a trigger, and clock means for providing system latch clock signals and system trigger clock signals, respectively, to each of said latch and said trigger comprising said latch pairs, said system being normally started with a system latch clock signal and stopped on a system trigger clock signal and further having an A scan clock signal to latches followed by a B scan clock signal to triggers of said latch pairs, a system for determining the propagation delay between any two of said latch pairs comprising:

means for initializing a latch and a trigger of an input latch pair to opposite states and a latch of an output latch pair to a state opposite said latch of said input latch pair;
means for providing a set bit to an output of said latch of said input latch pair;
means for operating said A and B scan clocks to scan in said set bit to said trigger of said input latch pair;
means for setting a cycle time between successive system trigger clock signals;
means for inhibiting a first system latch clock signal at said latch of said input latch pair allowing a first system trigger clock signal to be first in time to launch said set bit from said trigger of said input latch pair and initiate the determination of said propagation delay;
means for inhibiting a second system trigger clock signal allowing said set bit to be received and held by said latch of said output latch pair;
and
means for operating said A and B scan clocks to scan out data from said latch of said output latch pair.

5 more elements

In a system having level sensitive scan delay latch pairs composed of a latch and a trigger, and clock means for providing system latch clock signals and system trigger clock signals, respectively, to each of said latch and said trigger comprising said latch pairs, said system being normally started with a system latch clock signal and stopped on a system trigger clock signal and further having an A scan clock signal to latches followed by a B scan clock signal to triggers of said latch pairs, a method for determining the propagation delay between any pair of said latch pairs comprising the steps of:

initializing a latch and a trigger of an input latch pair to opposite states and a latch of an output latch pair to a state opposite said latch of said input latch pair;
providing a set bit to an output of said latch of said input latch pair;
operating said A and B scan clocks to scan in said set bit to said trigger of said input latch pair;
setting a cycle time between successive system rigger clock signals;
inhibiting a first system latch clock signal at said latch of said input latch pair allowing a first system trigger clock signal to be first in time to launch said set bit from said trigger of said input latch pair and initiate the determination of said propagation delay;
inhibiting a second system trigger clock signal allowing said set bit to be received and held by said latch of said output latch pair;
and
operating said A and B scan clocks to scan out data from said latch of said output latch pair.

5 more elements

Dependencies are inferred from the claim text.