Serial access semiconductor memory device having a redundancy system

A semiconductor memory device comprising,

• a plurality of memory cells arranged in a two-dimensional matrix array of rows and columns,
• column redundancy means for storing data in lieu of a defective memory cell of the array, being located adjacent the array, having a plurality of columns of memory cells,
• selecting means for selecting one of the rows of the array and the column redundancy means simultaneously to output data from the array and the column redundancy means in parallel in responsive to a readout address signal,
• a data buffer for storing parallel data from the array,
• a redundant data buffer for storing parallel data from the column redundancy means,
• a read only memory in which the defective address signal according to the defective memory cell is stored,
• comparing means for comparing the defective memory address signal from the read only memory with the readout address signal, and generating a switching control signal and a redundant selector control signal,
• parallel-serial converting means for inputting the data from the data buffer and the redundant data buffer and for outputting the data in series, comprising;
• a plurality of flip-flop circuits connected in series, in which the final stage of the flip-flop circuits outputs the data in series, and a plurality of selectors for selecting data from the array and from the flip-flop circuits, being provided between the flip-flop circuits, wherein one of the selectors which is associated with the final stage selects the data from the column redundancy means, the data from the array and the data from the flip-flop circuits in responsive to the switching control signal, and
• a redundant selector for selecting the data from the parallel data of the redundant buffer corresponding to the redundant selector control signal to output to the selector being associated with the final stage.