Refresh control circuit of pseudo static random access memory and pseudo static random access memory apparatus

#The present invention relates to a refresh control circuit used for refreshing a pseudo static random access memory, and a pseudo static random access memory apparatus using the refresh control circuit.

#A pseudo static random access memory (PSRAM) has been developed recently, and the demand for PSRAMs is becoming extensive. A PSRAM uses as its memory cell a dynamic type memory cell constructed of one transistor and one capacitor used in a dynamic random access memory (DRAM), and uses as its peripheral circuit a peripheral circuit used in a static random access memory (SRAM). By virtue of such a circuit arrangement, a PSRAM has both the characteristics of DRAMs and SRAMs, i.e., the low cost and large capacity of a DRAM and the ease of use of a SRAM.

#As described above, a PSRAM uses a dynamic memory cell the same as that of a DRAM. Therefore, a refresh operation is required to hold data stored in this memory cell. In order to facilitate refresh operation control, a memory device is provided with a refresh control terminal RFSH. By using a refresh signal, the PSRAMs now available on the market are refreshed while they are not being accessed.

#FIG. 1 is a block diagram showing an embodiment of a refresh control circuit according to the present invention;

#FIG. 2 is a timing chart showing the operation of the refresh control circuit;

#FIG. 3 is a circuit diagram showing a particular example of the refresh control circuit;

#FIGS. 1 and 2 are a block diagram and timing chart of a refresh control circuit according to an embodiment of this invention. A memory request signal MREQ shown in FIG. 2(a) from an MPU is inputted to a change detection circuit (refresh control signal output circuit) and a delay circuit 12 in parallel. The change detection circuit 11 outputs a signal as shown in FIG. 2(c) which operates as an output-control/refresh-control signal OE/RFSH. The delay circuit 12 outputs a signal as shown in FIG. 2(b) which operates as a chip enable signal CE of a PSRAM. The following relationship stands for the signals shown in FIGS. 2(a) to 2(c). Namely, the signal MREQ shown in FIG. 2(a) delayed by a predetermined time is the signal CE shown in FIG. 2(b). As the signal MREQ shown in FIG. 2(a) changes its level from high (H) to how (L) or from L to H, the signal OE/RFSH shown in FIG. 2(c) changes from L to H, and after the lapse of a predetermined time, returns to L.

#The operation of the circuit shown in FIG. 1 will be described in more detail with reference to FIG. 2. As the level of the signal MREQ sown in FIG. 2(a) and supplied from MPU changes from H to L at time t0, the signal OE/RFSH of PSRAM shown in FIG. 2(c) changes its level from L to H at time t1, and thereafter changes its level from H to L at time t3. At time t2 between times t1 and t3, the signal CE of PSRAM shown in FIG. 2(b) changes its level from H to L. Then, during the selection state of PSRAM at time t3, the signal OE/RFSH changes its level from H to L, so the read or write operation for PSRAM is carried out. Specifically, if a write signal WR is supplied from MPU, a write operation is carried out, whereas if not, a read operation is carried out.

#As the signal MREQ shown in FIG. 2(a) and supplied from MPU changes its level from L to H at time t4, the signal OE/RFSH of PSRAM shown in FIG. 2(c) changes its level from L to H at time 55, and thereafter at time t7 changes its level from H to L. At time t6 between times t5 and t7, the signal CE of PSRAM shown in FIG. 2(b) changes its level from L to H. Then, during a non-selection state of PSRAM at time t7, the signal OE/RFSH changes its level from H to L, so as refresh operation of PSRAM is carried out. As can be understood from the above circuit operation, each time PSRAM is accessed, a refresh operation is necessarily performed after the access. Therefore, an additional refresh control circuit is not needed if the circuit shown in FIG. 2 is used.