Special carry save adder for high speed iterative division

A carry save adder for operation in conjunction with a quotient prediction logic circuit, said quotient prediction logic circuit providing quotient prediction logic signals, and also in conjunction with circuitry carrying true functions of a plurality of values and complement functions of a plurality of values, said plurality of values provided so as to be processed by said carry save adder, said carry save adder comprising:

• means for receiving said quotient prediction logic signals from said quotient prediction logic circuit;
• means for receiving partial remainder sum signals;
• means for receiving partial remainder carry signals;
• means for receiving said true functions of said plurality of values;
• means for receiving said complement functions of said plurality of values;
• means for manipulating said received true functions, complement functions, partial remainder sum signals, and partial remainder carry signals to produce all possible additions that may be made therefrom;
• and
• means for selecting a proper one of said all possible additions, said means for selecting comprising a multiplexing means connected serially in circuit with said means for manipulating, said multiplexing means also connected in circuit so as to receive said quotient prediction logic signals which direct said means for selecting to said proper one of all possible additions, and said multiplexing means also connected in a feed back loop type of connection with said quotient prediction logic circuit, whereby the operation of the carry save adder and the operation of the quotient prediction logic circuit are overlapped to speed their combined operation.