Decimation circuit employing multiple memory data shifting section and multiple arithmetic logic unit section

A dual decimation circuit configuration having first and second input data lines, comprising:

• a first decimation section including:
• a first forward shifting data section receiving input data samples in order from the first input data line including a plurality of forward decimation registers coupled in series, each forward decimation register having an input and an output, said forward decimation registers having a decimation depth and operating as FIFO registers;
• a first reverse shifting data section including a plurality of reverse decimation registers coupled in series with each reverse decimation register having an input, output and a decimation depth, a first of said reverse decimation registers being operable as at least one of a paintbrush LIFO register and a FIFO register, wherein each of the other reverse decimation registers operate as FIFO registers;
• a first plurality of arithmetic logic units (ALUs) having two inputs and an output, each first ALU having a first of said two inputs coupling with the output of one of said reverse decimation registers and a second of said two inputs coupling with the input of one of said forward decimation registers;
• a second decimation section including:
• a second forward shifting data section including a plurality of forward decimation registers coupled in series, each forward decimation register having an input and an output, said forward decimation registers having a decimation depth and operating as FIFO registers;
• a second reverse shifting data section including a plurality of reverse decimation registers coupled in series with each reverse decimation register having an input, output and a decimation depth, a first of said reverse decimation registers, which receives sequenced data samples in blocks from one of said forward decimation registers in the second decimation section, operates as a paintbrush LIFO register to reverse sequence said data samples within the blocks, said blocks having a size corresponding to a decimation factor, wherein each of the other reverse decimation registers operate as FIFO registers;
• a second plurality of ALUs having two inputs and an output, each second ALU having a first of said two inputs coupling with the output of one of said reverse decimation registers and a second of said two inputs coupling with the input of one of said forward decimation registers;
• and
• means for multiplexing connections within and between said first and second decimation circuits to form various configurations of the dual decimation circuit.

A decimating memory, comprising:

• a memory having addressable memory locations, said memory forming a plurality of registers, each of said registers including at least one addressable memory location;
• said plurality of registers form a forward shifting data section and a reverse shifting data section;
• a first decoder operating said registers in the forward shifting data section and all but a first of said registers in the reverse shifting data section as FIFO registers via read and write addressing of said addressable memory locations to input and output data samples, said read and write addressing of said addressable memory locations being offset with respect to one another to provide a decimation factor;
• a paintbrush decoder operating said first register in the reverse shifting data section as a LIFO register for reverse sequencing data samples within blocks of data samples received from said forward shifting data section, each of said registers in the forward shifting and reverse shifting data section providing an output;
• and
• an ALU section operating on said outputs and providing a decimating memory output.

A method of operating decimation circuitry for a digital filter, the method comprising the steps of:

• receiving data samples in forward shifting data section having a plurality of forward decimation registers coupled in-line;
• operating said forward decimation registers as FIFO registers of a certain decimation depth;
• providing an output from one of said forward decimation registers as an input to a first decimation register in a reverse shifting data section having a plurality of reverse decimation registers;
• operating said first decimation register in the reverse shifting data section as a LIFO register and the other reverse decimation registers as FIFO registers;
• reversing the order of data samples within blocks of data samples received in the first decimation register, said blocks having a size corresponding to the decimation depth;
• passing in-line the reversed data samples within blocks from the first decimation register to said reverse FIFO registers;
• providing a decimation output from each of the plurality of forward decimation registers and reverse decimation registers;
• and
• operating on said decimation outputs to provide an ALU combination of forward and reverse sequenced data samples.