Pipelined circuitry for allowing the comparison of the relative difference between two asynchronous pointers and a programmable value

A FIFO memory containing a block of circuitry for generating an output signal related to the fullness or emptiness of said FIFO memory, said block of circuitry comprising:

• (a) a first counter for generating a read clock signal corresponding to the number of read clock pulses received by said FIFO memory, the read clock signal comprising a read pulse count, and a second counter for generating a write clock signal corresponding to the number of write pulses received by said FIFO memory, the write clock signal commprising a write pulse count;
• (b) a subtractor circuit for producing true and complement difference signals corresponding to the difference of the read pulse count of said first counter and the write pulse count of said second counter, said true and complement difference signals each having first and second logic states corresponding to equal and unequal pulse counts, respectively;
• (c) a comparator circuit having true and complement signal inputs for comparing the logic state of a selected one of said true and complement difference signals to the logic value of a predetermined binary number, and for generating a compare output signal having a logic level indicative of the count difference between the first and second counters;
• (d) a program selector circuit interposed between said subtractor circuit and said comparator circuit for selectively connecting and cross connecting the true and complement difference signals to the true input and complement input of said comparator, respectively, according to the logic state of said predetermined binary number;
• (e) a blanking circuit for providing a blanking output signal having a first logic state in response to a predetermined logical transition of one of said clock signals;
• and,
• (f) means for generating a flag status bit having a logic level corresponding to the logic level of the compare output signal in response to a predetermined logical transition of the blanking output signal.

A FIFO memory containing a block of circuitry for generating an output signal related to the fullness or emptiness of said FIFO memory, said block of circuitry comprising:

• (a) a first counter for generating a read clock signal corresponding to the number of red clock pulses received by said FIFO memory, the read clock signal comprising a read pulse count, and a second counter for generating a write clock signal corresponding to the number of write pulses received by said FIFO memory, the write clock signal commprising a write pulse count;
• (b) a subtractor circuit for producing true and complement difference signals corresponding to the difference of the read pulse count of said first counter and the write pulse count of said second counter, said true and complement difference signals each having first and second logic states corresponding to equal and unequal pulse counts, respectively;
• (c) a comparator circuit having true and complement signal inputs for comparing the logic state of a selected one of said true and complement difference signals to the logic value of a predetermined binary number, and for generating a compare output signal having a logic level indicative of the count difference between the first and second counters;
• (d) a program selector circuit interposed between said subtractor circuit and said comparator circuit for selectively connecting and cross connecting the true and complement difference signals to the true input and complement input of said comparator, respectively, according to the logic state of said predetermined binary number;
• (e) a blanking circuit for providing a blanking output signal having a first logic state in response to a predetermined logical transition of one of said clock signals, and said blanking output signal having a second logic state in the absence of a clock signal logical transition;
• and,
• (f) a latch circuit having a data signal input coupled to the compare output signal, a clock signal input coupled to the blanking output signal, and a data output node, said latch circuit being operable to store a flag status bit on the data output node in response to a logical transition of the blanking output signal.

A method for producing an output signal indicative of the difference between two asynchronous clock signals relative to a predetermined binary number comprising the steps:

• (a) counting the number of first clock pulses of said first clock signal in a first counter, and the number of second clock pulses of said second clock pulses of said second clock signal in a second counter;
• (b) subtracting the count of said first counter from the count of said second counter and producing true and complement difference signals, each difference signal having first and second logic states corresponding to equal and unequal clock counts, respectively;
• (c) comparing the logic state of each bit of a selected one of the true and complement difference signals generated in step (b) to the logic state of each corresponding bit, respectively, of said predetermined binary number;
• (d) causing said output signal to be a first logic state if the bit logic states of the selected difference signal are the same, respectively, as the bit logic states of said predetermined binary number, and causing said output signal to be a second logic state if the bit logic states of the selected difference signal are not the same, respectively, as the logic states of said predetermined binary number;
• (e) generating a flag status bit having a logic level corresponding to the logic level of the compare output signal in response to a predetermined logical transition of the blanking output signal;
• and,
• (f) storing the flag status signal bit on a data output node until the next occurrence of the predetermined logical transition.

A method for producing a flag output signal indicative of the difference between a first clock signal and a second clock signal relative to a program value of a predetermined binary number, comprising the steps:

• (a) counting the number of first clock pulses of said first clock signal, and counting the number of second clock pulses of said second clock signal;
• (b) producing true and complement difference signals corresponding to the difference of the count of said first counter and the count of said second counter, said true and complement difference signals each having first and second logic states corresponding to equal and unequal clock counts, respectively;
• (c) comparing the logic state of each bit of a selected one of true and complement difference signals to the logic state of each corresponding bit, respectively, of the program value of said predetermined binary number and producing a compare output signal having a first logic level if the program value of the binary number is greater than the count difference between the first and second counters and having a second logic level if the program value is equal to or less than said count difference;
• (d) selectively connecting the true and complement difference signals to the true input and complement input of said comparator, respectively, when said predetermined binary number is in a first logic state, and for selectively connecting said true and complement difference signals to the complement input and true input of said comparator circuit, respectively, when said predetermined binary number is in a second logic state;
• (e) providing a blanking output signal having a first logic state in response to a predetermined logical transition of one of said clock signals, and said blanking output signal having a second logic state in the absence of a clock signal logical transition;
• and,
• (f) generating a flag status bit on a data output node, the flag status bit having a logic level corresponding to the logic level of the compare output signal in response to a predetermined logical transition of the blanking output signal;
• and,
• (g) storing the flag status signal bit on the data output node until the next occurrence of the predetermined logical transition.