In a picture-in-picture-type color television or video-tape-recorder system having a synchronizing separator, a chroma circuit and a microcomputer, a circuit for moving rotationally a plurality of subordinate pictures, said circuit, comprising:
- memory means for storing video digital data, said video digital data being written onto or read from said memory means through dual ports;
- read/write controller means for generating a first control signal to control a start of writing or reading subordinate picture data onto or from said memory means and a second control signal to select an address for writing or reading said subordinate picture data onto or from said memory means, said read/write controller means receiving mode selecting data, a clock pulse control signal, and a strobe control signal from the microcomputer and main and subordinate picture vertical synchronizing signals separated by a synchronizing separator, said subordinate picture vertical synchronizing signal being used when said subordinate picture data is written onto said memory means, said main picture vertical synchronizing signal being used when said subordinate picture data is read from said memory means;
- time interval controller means for receiving a recognition signal for moving rotatably two selected subordinate pictures from a plurality of subordinate pictures and said main picture vertical synchronizing signal to control generation of said first and second control signals for writing and reading said subordinate picture data onto and from said memory means and a third control signal to maintain a fixed time interval between the movements of the two subordinate pictures, said time interval controller means being connected with said read/write controller means;
- switching means for switching sequentially and transmitting sequentially analog video chrominance signals for brightness, red, and blue of the two subordinate pictures, said chrominance signals being separated by a chroma circuit;
- analog/digital converter means for receiving the analog video chrominance signals from said switching means and for converting the analog video chrominance signals into video digital data;
- first data converting and latching means for converting and latching video digital data of said analog/digital converter means into a fixed bit adapted to be stored into said memory means;
- writing clock pulse and writing address signal generator means for generating switching signals to control the sequential transmission of said analog video chrominance signals of said switching means, for generating a sampling signal for the digital data conversion by said analog/digital converter means, for generating a first clock pulse for the converting and latching of said first data converting and latching means, for generating a second clock pulse for refreshing the writing, address and control of said memory means, upon receiving said first control signal to control the start of the writing of said read/write controller means, second basic frequency and the subordinate picture vertical and horizontal synchronizing signals being separated by said synchronizing separator;
- second data converting and latching means for converting the data read from said memory means into a form adapted for first to third digital/analog data;
- first to third digital/analog converter means for converting into analog output signals the first to third digital/analog data received from said second data converting and latching means;
- reading clock pulse and reading address signal generator means for generating a reading address signal, a latching clock pulse for the data conversion of said second data converting and latching means, and a third clock pulse for said first to third digital/analog converter means for converting the data into picture-in-picture analog signals by receiving said first control signal to control the start of the reading from said read/write controller means, first basic frequency supplied to a timing clock and the main picture horizontal and vertical synchronizing signals being separated by said synchronizing separator;
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- memory control timing and address selecting means for selecting a writing and reading address on a basis of the second clock pulse of said writing clock pulse and writing address signal generator means and the reading address signal of said reading clock pulse and reading address signal generator respectively, according to the first control signal received from said read/write controller means.