US 5,206,602 A · Biomedical amplifier circuit

Abstract

A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Drawings

Drawings are temporarily unavailable. Open the PDF at USPTO

Drawings

Claims6

Dependent claims

An electronic differential amplifier circuit comprising;

first stage amplifier means for receiving an input voltage and a gain feedback voltage and for generating a pair of first stage outputs by differentially amplifying said input voltage and said gain feedback voltage;
wherein said first stage amplifier means is chopper stabilized;
and
second stage amplifier means for receiving said pair of first stage outputs and for generating a pair of second stage outputs by differentially amplifying said pair of first stage outputs;
wherein said pair of second stage outputs further comprise a negative gain second stage output and a positive gain second stage output;
and
second stage common mode feedback means for receiving said pair of second stage outputs and for generating an average voltage by summing said pair of second stage outputs and for generating a second stage common mode feedback voltage by differentially amplifying said average voltage and a ground voltage;
wherein said second stage common mode feedback means is chopper stabilized;
and
gain feedback means for receiving said negative gain second stage output and for generating said gain feedback voltage by forming a fraction of said negative gain second stage output.

7 more elements

An electronic differential amplifier circuit comprising:

first chopper means for receiving an input voltage and a gain feedback voltage and for generating a pair of first chopper outputs by chopping said input voltage and said gain feedback voltage;
and
first stage signal amplifier means for receiving said pair of first chopper outputs and for generating a pair of first stage outputs by differentially amplifying said pair of first chipper outputs;
wherein said first stage signal amplifier means has a first stage common bias current;
and
first stage common mode feedback amplifier means for receiving said pair of first stage outputs and a first reference voltage and for generating a first average by summing said pair of first stage outputs and for generating a first stage common mode bias feedback voltage by differentially amplifying said first average and said first reference voltage;
wherein said first stage common mode bias feedback voltage controls said first stage common bias current;
and
second chopper means for receiving said pair of first stage outputs and for generating a pair of second chopper outputs by chopping said pair of first stage outputs;
wherein said second chopper means is synchronous with said first chopper means;
and
second stage signal amplifier means for receiving said pair of second chopper outputs and for generating a pair of second stage outputs by differentially amplifying said pair of second chopper outputs;
wherein said pair of second stage outputs further comprise a negative gain second stage output and a positive gain second stage output;
and
wherein said second stage signal amplifier means has a pair of variable output loads;
and
third chopper means for receiving said second stage outputs and a ground voltage and for generating a second average by summing said pair of second stage outputs and for generating a pair of third chopper outputs by chopping said second average and said ground voltage;
and
second stage common mode feedback amplifier means receiving said pair of third chopper outputs and for generating a pair of second stage common mode feedback voltages by differentially amplifying said pair of third chopper outputs;
and
fourth chopper means for receiving said pair of second stage common mode feedback voltages and for generating a pair of fourth chopper outputs by chopping said pair of second stage common mode feedback voltages;
and
current mirror means for receiving said pair of fourth chopper outputs and for converting said pair of fourth chopper outputs to a second stage load control voltage;
wherein said second stage load control voltage controls said pair of variable output loads;
and
gain feedback means for receiving said negative gain second stage output and for generating said gain feedback voltage by forming a fraction of said negative gain second stage output.

23 more elements

An electronic differential amplifier circuit comprising:

first and second input voltages;
and
first and second input transistors, each having a source connected to a first supply voltage and a gate connected to said first input voltage;
and
third and fourth input transistors, each having a source connected to said first supply voltage and a gate connected to said second input voltage;
and
a first output voltage connected to a drain of said second input transistor and to a drain of a first variable load transistor and to a drain of a first common feedback transistor;
and
a second output voltage connected to a drain of said fourth input transistor and to a drain of a second variable load transistor and to a drain of a second common feedback transistor;
and
wherein a drain of said first input transistor is connected to a first input current source load and to a gate of said second variable load transistor;
and
wherein a drain of said second input transistor is connected to a second input current source load and to a gate of said first variable load transistor;
and
wherein a source of said first and second variable load transistors and said first and second common feedback transistors is connected to a second supply voltage;
and
averaging means for receiving said first and second output voltages and for generating an average output voltage by summing said first and second output voltages;
and
first chopper means for receiving said average voltage and a ground voltage and for generating first and second chopper outputs by chopping said average output voltage and said ground voltage;
and
first feedback amplifier transistor having a source connected to a feedback amplifier common bias current source and a gate connected to said first chopper output;
and
second feedback amplifier transistor having a source connected to said feedback amplifier common bias current source and a gate connected to said second chopper output;
and
a first feedback output connected to a drain of said first feedback amplifier transistor and to a first feedback current source load and to a drain of a first feedback variable current source load and to a gate of a second feedback variable load;
and
a second feedback output connected to a drain of said second feedback amplifier transistor and to a second feedback current source load and to a drain of said second feedback variable current source load and to a gate of said first feedback variable load;
and
wherein a source of said first and second feedback variable current source loads is connected to said first supply voltage;
and
second chopper means for receiving said first and second feedback outputs and for generating a pair of second chopper outputs by amplifying and chopping said first and second feedback outputs;
and
current mirror means for receiving said pair of second chopper outputs and for generating a common feedback voltage from said pair of second chopper outputs;
wherein said common feedback voltage is connected to a gate of said first and second common feedback transistors.

31 more elements

Dependencies are inferred from the claim text.

Description14,810 words

Summary1,282 words

#U.S. Ser. No. 07/876,645, filed Apr. 30, 1992, Integrated Circuit for Physiological Measurement, by Richard Albert Baumgartner, Charles Everett Moore, and Earl Clark Herleikson.

#U.S. Ser. No. 07/876,611, filed Apr. 30, 1992, Analog to Digital Converter with Autoranging Offset, by Richard Albert Baumgartner, Charles Everett Moore, and Earl Clark Herleikson.

#U.S. Ser. No. 07/876,841, filed Apr. 30, 1992, Signal Processing Circuits with Digital Programmability, by Richard Albert Baumgartner and Earl Clark Herleikson.

Brief description of the drawings24 figures

#FIG. 1 is a schematic representation of a patient connected to an electrocardiograph system which includes the present invention.

#FIG. 2 is a schematic representation of a patient connected to a defibrillator system which includes the present invention.

#FIG. 3 is a schematic block diagram of the present invention along with some associated external circuitry.

Detailed description13,088 words

#I. Overview

#II. Analog Input Amplifiers

#III. Analog to Digital Conversion

Facts

Application

07/876,612Filed 30 Apr 1992

Granted

27 Apr 1993

Term ended

30 Apr 2012

Estimated · how

Pre-1995 term; greater of 17 years from grant or 20 years from filing when eligible. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification17 codes

A61B 5/308
Specially adapted for particular uses: for electrocardiography [ECG]
A61B 5/305
Input circuits therefor: common mode rejection
A61B 5/7203
Signal processing specially adapted for physiological signals or for diagnostic purposes: for noise prevention, reduction or removal
H03F 3/45188
Long tailed pairs: non-folded cascode stages

Biomedical amplifier circuit

Life of this patent

Biomedical amplifier circuit

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims6

Description14,810 words

Drawings

Classification17 codes

Life of this patent

Description14,810 words