Methods for testing integrated circuit devices

A method for testing an integrated circuit chip comprising the steps of:

• making an array of solder bumps on one surface of the integrated circuit chip, at least certain ones of the solder bumps having center-to-center spacings of less than about fifteen mils;
• interconnecting at least certain ones of the solder bumps to at least certain ones of conductor pads of a test fixture;
• said interconnecting step comprising the steps of, first, placing on the conductor pads a layer of anisotropic conductive material comprising a plurality of columns of conductive particles each extending across the thickness of the layer, second, placing the integrated circuit chip on the anisotropic conductive layer with the solder bumps contacting the anisotropic conductive layer, and third, compressing the integrated circuit chip against the anisotropic conductive layer with sufficient force to establish electrical interconnection between at least certain ones of said solder bumps and at least certain ones of the conductor pads by way of at least certain ones of said columns of conductive particles;
• and testing the integrated circuit chip comprising the step of directing electrical current through the integrated circuit chip, at least some of the solder bumps, at least some of the columns of conductive particles, and at least some of the test fixture conductor pads;
• wherein, prior to the interconnecting step, each solder bump is inserted through an aperture in a spacer member, the spacer member having a smaller thickness than the length of each solder bump, thereby to reduce the physical distortion of the anisotropic layer during the compression step and reducing the likelihood of spurious breakdown between adjacent conductive columns.