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AssigneeInternational Business Machines Corporation
InventorsJames W. Dawson, George A. DeLuca, Michael Nicewicz
Estimating the term…
On-chip circuitry facilitates fuse testing in customized integrated circuits. The circuitry has specific application in testing fuse redundancy high end memories. A latch assisted fuse testing (LAFT) methodology employs an on-chip latch stack which can be used in place of the fuses. The latches in the stack are programmable and can perform the same function as the fuses during chip operation. This allows testing or experimentation to be performed nondestructively, without blowing any fuses. In one particular application of the invention, memory arrays with redundant blocks on a chip are provided with the on-chip latch stack. After the tests based on previously generated error data are performed using the latch stack, fuses are blown to repair the memory array by replacing defective memory blocks with redundant blocks.
A latch assisted fuse testing method for testing integrated circuit chips during the process of manufacturing said chips, said chips being fabricated with an array structure characterized by a main array structure and redundant blocks wherein redundant blocks can be substituted for blocks in said main array structure by the selective blowing of fuses in a fuse array, said testing method comprising the steps of:
The latch assisted fuse testing method recited in claim 6 wherein the step of blowing fuses is performed by supplying a current to blow those fuses according to the programming of said latches.
An integrated circuit chip comprising:
Dependencies are inferred from the claim text.