Sense amplifier for non-volatile semiconductor storage device
AssigneeNEC Corporation
InventorShinichi Iwashita
Life of this patent
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Abstract
A sense amplifier for a non-volatile semiconductor storage device includes a true and a complementary load circuit which are for holding the potentials of input signals and which have the current driving capability lower than that of each memory cell of the semiconductor storage device. These true and complementary load circuits are connected with a true and a complementary input terminal of the conventional sense amplifier. In accordance with the output logical value of the sense amplifier, if it is in the "H" level, the complementary load circuit is activated whereas if it is in the "L" level, the true load circuit is activated. In this way, the operation speed of the sense amplifier at a memory cell selecting operation can be effectively improved.
Claims5
A sense amplifier for a non-volatile semiconductor storage device having a plurality of memory cells in a memory cell array, said sense amplifier comprising:
- a true and a complementary input terminal (TI, TII) for receiving a true and a complementary input signal (SI, SII) from said memory cells;
- first and second current mirror circuits (13,14) which amplify and detect said true and said complementary input signal from said memory cells, respectively;
- a true and a complementary input signal stabilizing circuit having input nodes connected to said true and complementary input terminals, respectively, and having output nodes connected to input nodes of said first and second current mirror circuits, respectively, for suppressing potential variations in said true and complementary input signals;
- true and complementary input signal potential holding means (16,17) which are connected with said true and said complementary input terminal, respectively, for holding potentials of the true and complementary input signals and having a current driving capability which is lower than the current driving capability of said memory cell in said memory cell array;
- and
- true and complementary sense signal producing circuit (IN3,IN4) for producing a true and a complementary sense signals which determine an operation or non-operation of said true and said complementary input signal potential holding means based on an output logical value of the sense amplifier.
Dependencies are inferred from the claim text.