High-speed programmable state counter

A method of generating an output signal when a predetermined count sequence matches a programmed input data pattern applied to a programmable state counter, comprising the steps of:

• generating the predetermined count sequence;
• combining first and second data inputs of each of a plurality of first flipflops as a logical exclusive-NOR operation for providing an output signal and an inverted output signal, said first data inputs receiving the programmed input data pattern, said second data inputs receiving the predetermined count sequence;
• applying said inverted outputs of a first portion of said plurality of first flipflops to a first data input of a second flipflop in a wired-OR configuration;
• applying said inverted outputs of a second portion of said plurality of first flipflops to a second data input of said second flipflop in a wired-OR configuration;
• and
• combining said first and second data inputs of said second flipflop as a logical OR operation for providing the output signal of the programmable state counter.

An integrated programmable state counter for generating an output signal when a predetermined count sequence matches a programmed input data pattern, comprising:

• first means for generating the predetermined count sequence at a plurality of outputs;
• a plurality of first flipflops each having first and second data inputs, an output and an inverted output, said first data inputs receiving the programmed input data pattern, said second data inputs being respectively coupled to said plurality of outputs of said first means, said first and second data inputs of each of said plurality of first flipflops combining as a logical exclusive-NOR operation for providing an output signal at said output of each of said plurality of first flipflops;
• and
• a second flipflop having first and second data inputs and an output, said first data input being wired-OR'ed to said inverted outputs of a first portion of said plurality of first flipflops, said second data input being wired-OR'ed to said inverted outputs of a second portion of said plurality of first flipflops, said first and second data inputs of said second flipflop combining as a logical OR operation for providing the output signal of the programmable state counter.