Field effect transistor
AssigneeSumitomo Electric Industries, Ltd.
InventorNobuhiro Kuwata
Life of this patent
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Abstract
There is disclosed a field effect transistor comprising a channel layer formed of GaInAs and provided with a planar dope layer doped with an impurity in the form of a two-dimensional thin plane a cap layer and a buffer layer formed respectively in contact with the upper and lower faces of the channel layer, the cap layer and buffer layer being formed of GaInAs whose In composition ratio is lower than that of the channel layer first and a second semiconductor layers formed respectively in contact with the cap layer and the buffer layer, first and second semiconductor layers being formed of GaInAs whose In composition ratio is lower than GaAs or the cap layer and the buffer layer.
Claims14
A field effect transistor comprising:
- a channel layer made of GaInAs and having a planar doped layer formed by impurity doping in a thin plane;
- a cap layer and a buffer layer formed of GaInAs so as to sandwich and contact said channel layer therebetween, said cap layer and said buffer layer having an In concentration lower than a minimum In concentration of said channel layer;
- a first semiconductor layer underlying said buffer layer and having an In concentration lower than a minimum In concentration of said buffer layer;
- and
- a second semiconductor layer formed on said cap layer and having an In concentration lower than a minimum In concentration of said cap layer.
Dependencies are inferred from the claim text.