Trench isolation process

A method of making an integrated circuit having active MOS devices and passive devices formed in a silicon wafer, comprising the steps of:

• forming a buried layer in selected regions of said silicon wafer, said buried layer being formed by doping with a predetermined buried layer dopant;
• forming surface isolation boundary regions in and below the surface of said silicon wafer about selected areas, by doping said silicon wafer with a predetermined surface isolation dopant of the same polarity as said buried layer dopant, for isolating said selected areas from one another;
• forming components of said active and passive devices in said silicon wafer;
• thereafter cutting a trench, having a sidewall, from said surface isolation boundary regions down through said silicon wafer to said buried layer;
• forming a sidewall liner on a sidewall of said trench by oxidizing said sidewall to a predetermined thickness of sidewall oxide and subsequently depositing a layer of sidewall nitride to a predetermined nitride thickness on said sidewall oxide;
• filling at least the upper portions of said trench with a temporary backfill material;
• depositing a cover layer above at least a portion of said trench, said cover layer being patterned to expose a portion of said temporary backfill through backfill removal apertures, and;
• removing at least a portion of said temporary backfill, whereby said trench is at least partially empty;
• and
• connecting said components to form an integrated circuit having said trench substantially empty.

A method of making an integrated circuit in an epitaxial layer on a silicon substrate containing both N and P channel MOS devices and bipolar NPN and PNP devices, the method comprising the steps of:

• doping said silicon substrate with a dopant of the type N-;
• forming one or more N-wells and one or more P-wells in said epitaxial layer;
• implanting a continuous buried layer region to be disposed below said epitaxial layer;
• implanting dopants in said epitaxial layer for one or more N-wells and for one or more P-wells for a MOS device, both said dopant for said N-wells and said dopant for said P-wells being P-type with said N-well dopant being implanted with a concentration sufficient to make the resistivity of said N-well greater than that of said epitaxial layer, but insufficient to change the polarity of said N-well to P-type;
• simultaneously implanting element regions for both said NPN and PNP devices and source regions and drain regions for said N-channel MOS devices;
• simultaneously implanting element regions for both said NPN and PNP devices and source regions and drain regions for said P-channel MOS devices;
• simultaneously diffusing said element regions for both said NPN and PNP devices, and said source and said drain regions;
• and
• thereafter forming contacts and completing said integrated circuit.

A method of making an integrated circuit in an epitaxial layer on a silicon substrate containing both N and P channel MOS devices and bipolar NPN and PNP devices comprising the steps of:

• implanting a continuous buried layer region having a buried layer dopant concentration below the sites of said NPN, PNP, N-channel and P-channel devices, said buried layer region to be disposed below said epitaxial layer, and then implanting dopants in said epitaxial layer for at least one well for an MOS device;
• forming field threshold adjustment regions in the upper portion of said epitaxial layer having a dopant concentration of about the same magnitude and of the same polarity as said buried layer dopant concentration;
• simultaneously implanting element regions for both said NPN and PNP devices and source regions and drain regions for said N-channel MOS devices;
• simultaneously implanting element regions for both said NPN and PNP devices and source regions and drain regions for said P-channel MOS devices;
• next, cutting a trench about said PNP, NPN, N-channel and P-channel devices from said field threshold adjustment regions down to said buried layer, whereby said devices are isolated from one another by said trenches;
• simultaneously diffusing said element regions for both said NPN and PNP devices, and said source and said drain regions;
• and
• thereafter forming contacts and completing said integrated circuit.