Method and apparatus for resetting a memory upon power recovery

In a data processing system including a memory for storing data, a power system for providing power to the data processing system, a battery back-up means for providing power to certain of the data processing system circuitry during power system interrupts when the power system is not providing power to the data processing system, and a system manager means for monitoring the power system and asserting a system reset signal when the power system provides power to the data processing system at initial system start-up and upon restoration of power from the power system to the data processing system after a power system interrupt, the memory including memory elements for storing the data and a memory controller including a memory control means for providing memory control signals for controlling operations of the memory and a refresh means including for providing refresh signals to the memory elements, the refresh means including a refresh clock for providing a refresh clock signal indicating refresh clock cycles and a refresh counter connected from the refresh clock and responsive to the refresh clock signal for counting refresh clock cycles and providing refresh signals corresponding to the refresh clock cycles to the memory elements, the memory control means of the memory controller being connected from the power system and the memory elements and the refresh means of the memory controller being connected from the power system and from the battery back-up means, a method for resetting the memory controller so that the memory control signals provided by the memory control means of the memory controller are in synchronization with the refresh signals provided by the refresh means when the power system provides power to the data processing system at initial system start-up and upon restoration of power from the power system to the data processing system after a power system interrupt, comprising the steps of:

• in state detection means connected from the refresh counter, detecting a change in count of the refresh counter to a count equivalent to a reset count of the refresh counter and asserting a state change signal, and
• in a memory controller reset means connected from the state detection means and connected from the system manager means and responsive to the state change signal and to the occurrence of the system reset signal, providing a memory controller reset signal to the memory controller, whereby
• the memory controller reset signal occurs in synchronization with the change of count of the refresh counter to the count equivalent to the refresh counter reset count, and
• the memory controller is responsive to the memory controller reset signal so that the memory control signals provided by the memory control means of the memory controller are in synchronization with the refresh signals provided by the refresh means.