Processor with preceding operation circuit connected to output of data register

A processor comprising:

• control signal generation means for generating a control signal to control the designation and execution of a first operation,
• first operating means responsive to the control signal for carrying out the first operation designated by the control signal,
• data bus lines connected to said first operating means for transmitting data used for the first operation by said first operating means,
• holding means connected to said data bus lines for holding data used for the first operation by said first operating means, and
• second operating means connected to an output of said holding means for carrying out a predetermined second operation,
• said holding means comprising a single register connected to said data bus lines for holding data used in said second operating means,
• said second operating means being responsive to the control signal to supply data indicative of the result of the second operation to said data bus lines, wherein said second operating means comprises sign inverter means connected to the output of said single register for inverting the sign of output data from said single register.

A processor comprising;

• control signal generation means for generating a control signal to control the designation and execution of a desired first operation,
• first operating means responsive to the control signal for carrying out the first operation designated by the control signal,
• data bus lines connected to said first operating means for transmitting data used for the first operation by said first operating means,
• holding means connected to said data bus lines for holding first data used for the first operation by said first operating means and responsive to said control signal to supply said data to said data bus lines,
• data storage means connected to said data bus lines for storing second data used for the first operation by said first operating means, and
• second operating means continuously receiving an output of said holding means and an output of said data storage means for carrying out a predetermined second operation in responsive to storage of said data in said holding means,
• said second operating means being responsive to the control signal to supply data indicative of the result of the second operation to said data bus lines.

A processor comprising:

• data bus lines for transmitting operational data,
• operating means connected to said data bus lines for operating on the operational data applied from said data bus lines,
• at least first and second holding means connected to receive output data from said operating means for holding the output data,
• adding means continuously receiving outputs of said first and second holding means for adding the data held in said first and second holding means, and
• subtracting means continuously receiving outputs of said first and second holding means for subtracting the data held in said first and second holding means, said adding means and subtracting means having outputs connected to said data bus lines.

In a digital signal processor including an instruction storage means, a program sequence control means responsive to instructions from said instruction storage means for generating control signals, data storage means, address means for addressing data in said data storage means and for generating source and destination addresses for operands and for results of mathematical operations on said operands, data operating means including multiplying means and ALU (arithmetic logic unit) means for performing mathematical operations on data supplied thereto, a plurality of register means for storage of intermediate results of said mathematical operations, and bus means for transfer of signals and data among the plurality of means of said digital signal processor, the improvement comprising:

• step reducing means for reducing a number of mathematical steps performed by said ALU means in obtaining a result of a predetermined mathematical operation, said step reducing means comprising:
• preceding operation means for performing a processing step on the intermediate result stored in said register means preliminary to provision of the intermediate result to said ALU means, thereby eliminating a requirement of said ALU means to perform said processing step and saving processing time required of said ALU means to execute said predetermined mathematical operation,
• said preceding operation means having input means continuously connected to at least one of said register means for continuously receiving said intermediate result therefrom,
• said preceding operation means initiating performance of said processing step substantially simultaneously with storage of said intermediate result in said register means connected to said input means thereof and responsive to control signals from said address means for transferring a result of said processing step performed thereby to said bus line for provision to said ALU means.