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US 5,204,957 AGranted
Integrated circuit timer with multiple channels and dedicated service processor
AssigneeMotorola, Inc.
InventorsBrian F. Wilkie, Vernon B. Goler, Stanley E. Groves, John J. Vaglica
Life of this patent
Estimating the term…
Abstract
A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.
Claims9
A microprocessor comprising:
- a first memory;
- a first bus coupled to the first memory;
- a first processing unit coupled to the first bus, the first processing unit is capable of executing instructions stored in the first memory;
- a second bus coupled to the first memory;
- and
- a timer unit, the timer unit further comprising:
- a) a second memory;
- b) a third bus coupled to the second memory;
- c) a second processing unit coupled to the second bus and to the third bus, the second processing unit is capable of executing instructions stored in the first memory and is also capable of executing instructions stored in the second memory;
- d) a third memory coupled to the first bus;
- e) a fourth bus coupled to the third memory and to the second processing unit;
- and
- f) timer logic, the timer logic further comprising:
- i) pin logic coupled to a pin of the microprocessor;
- ii) an event register coupled to the pin logic;
- and
- iii) a fifth bus coupled to the event register and to the second processing unit.
14 more elements
A microprocessor comprising:
- a first memory;
- a first bus coupled to the first memory;
- a first processing unit coupled to the first bus, the first processing unit is capable of executing instructions stored in the first memory;
- a second bus coupled to the first memory;
- and
- a timer unit, the timer unit further comprising:
- a) a second memory;
- b) a third bus coupled to the second memory;
- c) a second processing unit coupled to the second bus and to the third bus, the second processing unit is capable of executing instructions stored in the first memory and is also capable of executing instructions stored in the second memory;
- d) a third memory coupled to the first bus;
- e) a fourth bus coupled to the third memory and to the second processing unit;
- and
- f) a plurality of timer channels, each of said plurality of timer channels further comprising:
- i) pin logic coupled to a pin of the microprocessor;
- ii) an event register coupled to the pin logic;
- and
- iii) a fifth bus coupled to the event register and to the second processing unit.
14 more elements
Dependencies are inferred from the claim text.