One clock address pipelining in segmentation unit

A microprocessor circuit for providing an address for each execution stage in a pipelined addressing system having pipelined stages for each instruction including a first decode stage, a second decode stage, a third execution stage, and a fourth writeback stage, said microprocessor circuit comprising

• first signal providing means for providing signals representing a displacement, a relative base address, and an index during said first decode stage;
• a combining means for combining the signals representing the displacement, the relative base address, and the index to provide an effective address during said second decode stage, said combining means coupled to said first signal providing means;
• second signal providing means for providing signals representing a segment base address during said first decode stage;
• a three input adder for combining the signals representing the displacement, the relative base address, the index, and the segment base address to provide a linear address during said second decode stage comprised of and three input adder, said three input adder coupled to said first signal providing means and said second signal providing means;
• means for providing the output of the combining means to an input of the three input adder;
• and
• third signal providing means for providing said effective address and said linear address during said third execution stage, said third signal providing means coupled to said combining means and said three input adder.