Multi-channel/multi-circuit communication controller

A multi-channel communication controller for use with a main computer utilizing a plurality of channels, the controller comprising:

• a plurality of subprocessor sections, each subprocessor section disposed for an associated channel of the plurality of channels to conduct communication processing, each said subprocessor section including a subprocessor CPU, a subprocessor serial controller, a subprocessor local bus for establishing connections between said subprocessor CPU and said subprocessor serial controller, and a subprocessor controller connected to said local bus;
• a main processor section for controlling said subprocessor sections, said main processor section including a main CPU, a main ROM, a main RAM, a main local bus for establishing connections between said main CPU, said main ROM, and said main RAM, and a main controller connected to said main local bus;
• an upper-level local bus connected to said main controller and each of the subprocessor controllers;
• and,
• a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of the main computer, said memory sharing section including a shared controller connected to said upper-level local bus and said system bus and a shared RAM connected to said shared controller,
• wherein each said subprocessor controller includes an address translating section for accomplishing an address translation on an address outputted from said CPU of said subprocessor section so as to transfer an address after the translation to said upper-level local bus.

An ISDN communication controller for use in a main computer, the controller comprising:

• a first subprocessor section for achieving communication processing on B channels, said first subprocessor section including a first CPU, a first RAM, a first serial controller connected to the B channels, a first local bus for establishing connections between said first CPU, said first RAM, and said first serial controller, and a first controller connected to said first local bus;
• a second subprocessor section for achieving communication processing on the B channels, said second subprocessor section including a second CPU, a second RAM, a second serial controller connected to the B channels, a second local bus for establishing connections between said second CPU, said second RAM, and said second serial controller, and a second controller connected to said second local bus;
• an LAPD processing section for achieving communication processing on a D channel, said LAPD processing section including a third CPU, a first ROM, a third serial controller connected to the D channel, a third local bus for establishing connections between said third CPU, said first ROM, and said third serial controller, and a third controller connected to said third local bus;
• a main processor section for controlling said first and second subprocessor sections and said LAPD processing section, said main processor section including a fourth CPU, a second ROM, a third RAM, a fourth local bus for establishing connections between said fourth CPU, said second ROM, said third RAM, and said fourth local bus, and a fourth controller connected to said fourth local bus;
• an upper-level local bus connected to said first, second, and fourth controllers;
• a line driver for multiplexing an ISDN line into the D and B channels, said D channel being connected to said third serial controller;
• a channel control section connected to said line driver, said first and second subprocessor sections, and said fourth local bus for operating under control of said main processor to connect said B channels to said first and second serial controllers such that said B channels can be changed over between said first and second controllers;
• and
• a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of said main computer, said memory sharing section including a controller connected to said upper-level local bus and said system bus and a shared RAM connected to said controller, wherein:
• said first controller includes a first address translating section for achieving a first address translation on a first address supplied from said main processor section via said upper-level local bus to transfer a first translated address after the first address translation to said first RAM;
• and
• said second controller includes a second address translating section for achieving a second address translation on a second address supplied from said main processor section via said upper-level local bus to transfer a second translated address after the second address translation to said second RAM.

An ISDN communication controller for use in a main computer, the controller comprising:

• a first subprocessor section for achieving communication processing on B channels, said first subprocessor section including a first CPU, a first serial controller connected to the B channels, a first local bus for establishing connections between said first CPU and said first serial controller, and a first controller connected to said first local bus;
• a second subprocessor section for achieving communication processing on the B channels, said second subprocessor section including a second CPU, a second serial controller connected to the B channels, a second local bus for establishing connections between said second CPU and said second serial controller, and a second controller connected to said second local bus;
• an LAPD processing section for achieving communication processing on a D channel, said LAPD processing section including a third CPU, a first ROM, a third serial controller connected to the D channel, a third local bus for establishing connections between said third CPU, said first ROM, and said third serial controller, and a third controller connected to said third local bus;
• a main processor section for controlling said first and second subprocessor sections and said LAPD processing section, said main processor section including a fourth CPU, a second ROM, an RAM, a fourth local bus for establishing connections between said fourth CPU, said second ROM, said RAM, and said fourth local bus, and a fourth controller connected to said fourth local bus;
• an upper-level local bus connected to said first, second, and fourth controllers;
• a line driver for multiplexing an ISDN line into the D and B channels, said D channel being connected to said third serial controller;
• a channel control section connected to said line driver, said first and second subprocessor sections, and said fourth local bus for operating under control of said main processor to connect said B channels to said first and second serial controllers such that said B channels can be changed over between said first and second controllers;
• and
• a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of said main computer, said memory sharing section including a controller connected to said upper-level local bus and said system bus and a shared RAM connected to said controller, wherein:
• said first controller includes a first address translating section for achieving a first address translation on a first address supplied from said first CPU via said upper-level local bus to transfer a first translated address after the first translation to said shared RAM;
• and
• said second controller includes a second address translating section for achieving a second address translation on a second address supplied from said second CPU via said upper-level local bus to transfer a second translated address after the second translation to said shared RAM.